From 39b2d78bce5896277db293b349fc006dd130b39a Mon Sep 17 00:00:00 2001
From: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
Date: Sun, 31 Jul 2022 14:19:11 +0300
Subject: [PATCH] econet: move common part of arcee/rodimus/en7523_evb dts to
en75xx-base.dtsi, fix spaces and tabs as well.
---
iopsys-econet/dts/arcee.dts | 2649 +++++++++++-----------------
iopsys-econet/dts/en7523_evb.dts | 485 +----
iopsys-econet/dts/en75xx-base.dtsi | 517 ++++++
iopsys-econet/dts/rodimus.dts | 587 +-----
4 files changed, 1649 insertions(+), 2589 deletions(-)
create mode 100755 iopsys-econet/dts/en75xx-base.dtsi
diff --git a/iopsys-econet/dts/arcee.dts b/iopsys-econet/dts/arcee.dts
index 63c9f747a..485c2de44 100755
--- a/iopsys-econet/dts/arcee.dts
+++ b/iopsys-econet/dts/arcee.dts
@@ -1,1614 +1,1083 @@
-
-
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
/dts-v1/;
-/ {
- compatible = "econet,en7523";
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <1>;
+#include "en75xx-base.dtsi"
- chosen {
+/ {
+ chosen {
bootargs = "root=/dev/mtdblock3 ro console=ttyS0,115200n8 earlycon init=/sbin/init";
stdout-path = &uart1;
};
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- atf-reserved-memory@80000000 {
- compatible = "econet,en7523-atf-reserved-memory";
- no-map;
- reg = <0x80000000 0x40000>;
+/* Generic led driver is not compatible yet
+ leds {
+ compatible = "gpio-leds";
+ led1 {
+ label = "green:led1";
+ gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
};
-
- npu_reserved: npu_binary@84000000 {
- no-map;
- reg = <0x84000000 0x100000>;
+ led2 {
+ label = "red:led2";
+ gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+ };
+ led3 {
+ label = "blue:led3";
+ gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
};
-
- /* pstore memory reservations */
- #include "en7523_pstore.dtsi"
-
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
};
+*/
+};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
+&pcie0 {
+ device_type = "pci";
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 1>,
+ <0 0 0 2 &pcie_intc0 2>,
+ <0 0 0 3 &pcie_intc0 3>,
+ <0 0 0 4 &pcie_intc0 4>;
+ pcie-port = <0>;
+ num-lanes = <1>;
+ status = "okay";
+
+ mt7915@0,0{
+ reg = <0x0000 0 0 0 0>;
+ power-limits{
+ r0{
+ regdomain = "etsi";
+ txpower-2g {
+ r1 {
+ channels = <1 1>;
+ txs_delta = <0 0 0>;
+ rates-cck = <30 30 30 30>;
+ rates-ofdm = <38 38 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 36 36 34 34 32 32 30 30>,
+ <1 37 37 36 36 34 34 32 32 30 30>,
+ <1 30 31 32 30 20 33 25 23 39 34>,
+ <1 24 26 36 28 31 33 23 33 21 25>;
+ rates-ru =
+ <1 20 20 18 18 16 16 14 14 12 12 10 10>,
+ <1 26 26 24 24 22 22 20 20 18 18 16 16>,
+ <1 32 32 30 30 28 28 26 26 24 24 22 22>,
+ <1 38 38 36 36 34 34 32 32 30 30 28 28>,
+ <1 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 23 34 23 35 38 24 26 38 28 29 24 34>,
+ <1 33 37 27 27 33 35 22 24 37 28 27 26>;
+ };
+ r2 {
+ channels = <2 2>;
+ txs_delta = <0 0 0>;
+ rates-cck = <30 30 30 30>;
+ rates-ofdm = <38 38 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 36 36 34 34 32 32 30 30>,
+ <1 37 37 36 36 34 34 32 32 30 30>,
+ <1 29 26 37 20 35 27 31 23 27 23>,
+ <1 28 33 25 28 27 23 24 33 24 21>;
+ rates-ru =
+ <1 20 20 18 18 16 16 14 14 12 12 10 10>,
+ <1 26 26 24 24 22 22 20 20 18 18 16 16>,
+ <1 32 32 30 30 28 28 26 26 24 24 22 22>,
+ <1 38 38 36 36 34 34 32 32 30 30 28 28>,
+ <1 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 28 22 29 39 21 39 29 24 23 32 25 21>,
+ <1 23 32 30 39 29 27 36 26 22 33 34 29>;
+ };
+ r3 {
+ channels = <3 3>;
+ txs_delta = <0 0 0>;
+ rates-cck = <31 31 31 31>;
+ rates-ofdm = <38 38 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 36 36 34 34 32 32 30 30>,
+ <1 37 37 36 36 34 34 32 32 30 30>,
+ <1 38 24 33 22 26 36 31 23 39 33>,
+ <1 33 34 34 35 22 28 21 35 35 33>;
+ rates-ru =
+ <1 20 20 18 18 16 16 14 14 12 12 10 10>,
+ <1 26 26 24 24 22 22 20 20 18 18 16 16>,
+ <1 32 32 30 30 28 28 26 26 24 24 22 22>,
+ <1 38 38 36 36 34 34 32 32 30 30 28 28>,
+ <1 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 38 34 33 32 37 30 28 22 36 28 31 30>,
+ <1 20 25 31 29 23 24 24 39 20 27 29 20>;
+ };
+ r4 {
+ channels = <4 4>;
+ txs_delta = <0 0 0>;
+ rates-cck = <31 31 31 31>;
+ rates-ofdm = <38 38 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 36 36 34 34 32 32 30 30>,
+ <1 37 37 36 36 34 34 32 32 30 30>,
+ <1 38 23 25 21 27 38 20 23 39 36>,
+ <1 23 24 20 26 37 31 29 30 22 36>;
+ rates-ru =
+ <1 20 20 18 18 16 16 14 14 12 12 10 10>,
+ <1 26 26 24 24 22 22 20 20 18 18 16 16>,
+ <1 32 32 30 30 28 28 26 26 24 24 22 22>,
+ <1 38 38 36 36 34 34 32 32 30 30 28 28>,
+ <1 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 37 34 38 35 35 39 38 26 39 37 24 34>,
+ <1 29 31 24 39 24 22 20 28 34 31 30 21>;
+ };
+ r5 {
+ channels = <5 5>;
+ txs_delta = <0 0 0>;
+ rates-cck = <31 31 31 31>;
+ rates-ofdm = <38 38 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 36 36 34 34 32 32 30 30>,
+ <1 37 37 36 36 34 34 32 32 30 30>,
+ <1 21 37 28 38 39 35 30 29 36 24>,
+ <1 30 22 37 34 37 32 34 27 27 31>;
+ rates-ru =
+ <1 20 20 18 18 16 16 14 14 12 12 10 10>,
+ <1 26 26 24 24 22 22 20 20 18 18 16 16>,
+ <1 32 32 30 30 28 28 26 26 24 24 22 22>,
+ <1 38 38 36 36 34 34 32 32 30 30 28 28>,
+ <1 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 38 33 36 39 24 24 24 36 29 37 21 29>,
+ <1 20 36 39 30 25 33 39 25 36 22 22 26>;
+ };
+ r6 {
+ channels = <6 6>;
+ txs_delta = <0 0 0>;
+ rates-cck = <31 31 31 31>;
+ rates-ofdm = <37 37 37 37 36 36 34 34>;
+ rates-mcs =
+ <2 37 37 36 36 34 34 32 32 30 30>,
+ <1 33 39 30 36 33 37 38 39 38 35>,
+ <1 29 23 22 36 23 21 28 35 36 33>;
+ rates-ru =
+ <1 19 19 18 18 16 16 14 14 12 12 10 10>,
+ <1 25 25 24 24 22 22 20 20 18 18 16 16>,
+ <1 31 31 30 30 28 28 26 26 24 24 22 22>,
+ <2 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 23 23 31 30 21 30 27 33 27 23 31 23>,
+ <1 39 36 25 24 38 36 24 30 29 39 21 22>;
+ };
+ r7 {
+ channels = <7 7>;
+ txs_delta = <0 0 0>;
+ rates-cck = <31 31 31 31>;
+ rates-ofdm = <37 37 37 37 36 36 34 34>;
+ rates-mcs =
+ <2 37 37 36 36 34 34 32 32 30 30>,
+ <1 22 29 34 29 20 28 37 32 28 38>,
+ <1 31 23 31 36 25 21 23 23 23 36>;
+ rates-ru =
+ <1 19 19 18 18 16 16 14 14 12 12 10 10>,
+ <1 25 25 24 24 22 22 20 20 18 18 16 16>,
+ <1 31 31 30 30 28 28 26 26 24 24 22 22>,
+ <2 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 34 24 28 32 24 39 21 39 25 39 34 21>,
+ <1 33 24 24 24 28 31 39 36 31 23 20 25>;
+ };
+ r8 {
+ channels = <8 8>;
+ txs_delta = <0 0 0>;
+ rates-cck = <31 31 31 31>;
+ rates-ofdm = <37 37 37 37 36 36 34 34>;
+ rates-mcs =
+ <2 37 37 36 36 34 34 32 32 30 30>,
+ <1 27 20 34 28 20 20 30 36 31 35>,
+ <1 37 20 34 38 35 28 20 32 21 25>;
+ rates-ru =
+ <1 19 19 18 18 16 16 14 14 12 12 10 10>,
+ <1 25 25 24 24 22 22 20 20 18 18 16 16>,
+ <1 31 31 30 30 28 28 26 26 24 24 22 22>,
+ <2 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 21 28 28 37 39 27 21 36 29 24 28 32>,
+ <1 26 27 22 28 32 20 30 26 29 28 31 38>;
+ };
+ r9 {
+ channels = <9 9>;
+ txs_delta = <0 0 0>;
+ rates-cck = <31 31 31 31>;
+ rates-ofdm = <37 37 37 37 36 36 34 34>;
+ rates-mcs =
+ <2 37 37 36 36 34 34 32 32 30 30>,
+ <1 25 25 27 35 32 35 20 30 32 37>,
+ <1 36 34 38 30 35 39 36 33 20 25>;
+ rates-ru =
+ <1 19 19 18 18 16 16 14 14 12 12 10 10>,
+ <1 25 25 24 24 22 22 20 20 18 18 16 16>,
+ <1 31 31 30 30 28 28 26 26 24 24 22 22>,
+ <2 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 37 22 30 38 26 27 28 23 28 31 26 39>,
+ <1 22 39 29 24 39 35 34 37 38 36 29 27>;
+ };
+ r10 {
+ channels = <10 10>;
+ txs_delta = <0 0 0>;
+ rates-cck = <31 31 31 31>;
+ rates-ofdm = <37 37 37 37 36 36 34 34>;
+ rates-mcs =
+ <2 37 37 36 36 34 34 32 32 30 30>,
+ <1 31 39 34 29 38 29 38 35 24 20>,
+ <1 36 34 25 32 32 28 39 25 35 24>;
+ rates-ru =
+ <1 19 19 18 18 16 16 14 14 12 12 10 10>,
+ <1 25 25 24 24 22 22 20 20 18 18 16 16>,
+ <1 31 31 30 30 28 28 26 26 24 24 22 22>,
+ <2 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 36 31 30 32 20 24 39 25 36 29 22 28>,
+ <1 32 28 37 35 24 25 20 38 35 33 29 27>;
+ };
+ r11 {
+ channels = <11 11>;
+ txs_delta = <0 0 0>;
+ rates-cck = <31 31 31 31>;
+ rates-ofdm = <37 37 37 37 36 36 34 34>;
+ rates-mcs =
+ <1 37 37 36 36 34 34 32 32 30 30>,
+ <1 36 36 36 36 34 34 32 32 30 30>,
+ <1 23 26 33 31 26 21 38 34 39 20>,
+ <1 29 30 22 31 34 33 28 34 24 20>;
+ rates-ru =
+ <1 19 19 18 18 16 16 14 14 12 12 10 10>,
+ <1 25 25 24 24 22 22 20 20 18 18 16 16>,
+ <1 31 31 30 30 28 28 26 26 24 24 22 22>,
+ <1 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 36 36 36 36 34 34 32 32 30 30 28 28>,
+ <1 29 24 30 33 37 39 36 36 29 36 24 26>,
+ <1 25 28 33 34 34 23 22 36 33 35 22 24>;
+ };
+ r12 {
+ channels = <12 12>;
+ txs_delta = <0 0 0>;
+ rates-cck = <31 31 31 31>;
+ rates-ofdm = <37 37 37 37 36 36 34 34>;
+ rates-mcs =
+ <1 37 37 36 36 34 34 32 32 30 30>,
+ <1 36 36 36 36 34 34 32 32 30 30>,
+ <1 20 36 37 24 24 29 34 27 31 24>,
+ <1 29 22 21 38 24 25 31 23 20 21>;
+ rates-ru =
+ <1 19 19 18 18 16 16 14 14 12 12 10 10>,
+ <1 25 25 24 24 22 22 20 20 18 18 16 16>,
+ <1 31 31 30 30 28 28 26 26 24 24 22 22>,
+ <1 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 36 36 36 36 34 34 32 32 30 30 28 28>,
+ <1 31 26 23 24 36 34 24 30 24 25 31 24>,
+ <1 35 23 20 39 28 25 24 30 34 33 32 32>;
+ };
+ r13 {
+ channels = <13 13>;
+ txs_delta = <0 0 0>;
+ rates-cck = <31 31 31 31>;
+ rates-ofdm = <37 37 37 37 36 36 34 34>;
+ rates-mcs =
+ <1 37 37 36 36 34 34 32 32 30 30>,
+ <1 36 36 36 36 34 34 32 32 30 30>,
+ <1 29 24 37 23 38 36 39 32 35 33>,
+ <1 21 26 33 29 27 28 34 36 23 32>;
+ rates-ru =
+ <1 19 19 18 18 16 16 14 14 12 12 10 10>,
+ <1 25 25 24 24 22 22 20 20 18 18 16 16>,
+ <1 31 31 30 30 28 28 26 26 24 24 22 22>,
+ <1 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 36 36 36 36 34 34 32 32 30 30 28 28>,
+ <1 34 34 36 28 28 35 30 34 24 32 27 36>,
+ <1 34 30 24 34 36 36 20 23 25 31 31 20>;
+ };
+ r14 {
+ channels = <14 14>;
+ txs_delta = <0 0 0>;
+ rates-cck = <31 31 31 31>;
+ rates-ofdm = <37 37 37 37 36 36 34 34>;
+ rates-mcs =
+ <1 37 37 36 36 34 34 32 32 30 30>,
+ <1 36 36 36 36 34 34 32 32 30 30>,
+ <1 38 29 37 27 28 24 32 37 33 22>,
+ <1 31 37 23 28 23 35 21 22 20 34>;
+ rates-ru =
+ <1 19 19 18 18 16 16 14 14 12 12 10 10>,
+ <1 25 25 24 24 22 22 20 20 18 18 16 16>,
+ <1 31 31 30 30 28 28 26 26 24 24 22 22>,
+ <1 37 37 36 36 34 34 32 32 30 30 28 28>,
+ <1 36 36 36 36 34 34 32 32 30 30 28 28>,
+ <1 30 28 21 29 34 23 32 31 24 26 36 30>,
+ <1 22 28 32 29 24 20 23 21 33 33 22 24>;
+ };
};
- core1 {
- cpu = <&cpu1>;
+ txpower-5g {
+ r1 {
+ channels = <184 184>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <36 30 24 34 24 21 25 37>;
+ rates-mcs =
+ <1 26 39 32 20 39 32 30 22 38 36>,
+ <1 25 26 30 26 28 21 31 22 31 22>,
+ <1 35 22 33 26 22 25 21 38 23 30>,
+ <1 34 29 20 37 33 32 39 30 26 22>;
+ rates-ru =
+ <1 27 28 21 34 34 33 25 23 36 39 27 31>,
+ <1 33 20 24 26 32 29 36 23 35 29 31 21>,
+ <1 21 33 34 29 23 26 22 20 29 28 36 23>,
+ <1 20 29 38 21 22 23 36 20 26 27 22 23>,
+ <1 28 38 24 25 30 25 34 39 23 21 36 26>,
+ <1 38 32 21 35 22 21 36 32 29 28 20 20>,
+ <1 26 38 39 27 34 38 29 39 30 26 26 36>;
+ };
+ r2 {
+ channels = <188 188>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <29 33 22 28 39 35 24 32>;
+ rates-mcs =
+ <1 39 33 38 34 26 35 28 38 33 31>,
+ <1 38 20 22 24 35 24 37 28 37 28>,
+ <1 31 23 26 28 21 33 37 35 32 31>,
+ <1 22 23 26 22 24 38 25 20 27 31>;
+ rates-ru =
+ <1 32 39 28 30 26 25 20 35 27 36 28 24>,
+ <1 37 32 35 34 34 21 20 28 39 35 20 28>,
+ <1 25 22 32 37 31 26 36 30 29 29 38 32>,
+ <1 29 24 39 29 34 29 27 31 27 39 26 39>,
+ <1 32 32 20 25 37 20 32 34 26 24 37 37>,
+ <1 32 25 20 21 34 36 34 39 23 37 31 35>,
+ <1 24 28 36 21 23 22 25 33 33 24 30 22>;
+ };
+ r3 {
+ channels = <192 192>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <34 33 23 36 22 22 29 38>;
+ rates-mcs =
+ <1 35 30 20 26 36 37 38 23 24 20>,
+ <1 24 22 31 32 32 36 33 30 27 30>,
+ <1 22 26 22 34 22 30 28 34 38 22>,
+ <1 33 35 23 22 31 37 35 37 23 36>;
+ rates-ru =
+ <1 24 23 24 21 23 29 37 32 20 37 36 29>,
+ <1 39 20 22 26 34 21 33 31 39 23 38 22>,
+ <1 38 33 27 37 26 39 22 27 20 27 37 39>,
+ <1 35 37 33 31 31 39 35 31 38 33 36 31>,
+ <1 21 32 32 25 32 34 39 37 27 25 39 29>,
+ <1 35 31 21 30 32 39 38 37 29 22 28 22>,
+ <1 38 38 27 38 20 22 38 22 22 34 30 28>;
+ };
+ r4 {
+ channels = <196 196>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <22 32 38 39 35 25 21 23>;
+ rates-mcs =
+ <1 35 38 34 21 30 25 32 23 29 37>,
+ <1 29 33 24 23 28 33 23 30 24 34>,
+ <1 28 23 21 33 39 38 39 27 38 22>,
+ <1 30 24 36 21 26 38 32 30 37 30>;
+ rates-ru =
+ <1 20 34 37 34 39 34 25 34 20 31 33 22>,
+ <1 27 34 33 30 24 24 22 29 37 35 34 26>,
+ <1 36 37 36 37 37 32 34 27 35 33 23 21>,
+ <1 24 29 28 20 27 34 28 29 35 24 36 39>,
+ <1 39 33 28 23 34 39 34 39 25 38 35 29>,
+ <1 25 32 32 20 29 37 27 22 37 26 29 33>,
+ <1 33 23 35 38 31 29 29 22 36 35 33 25>;
+ };
+ r5 {
+ channels = <8 8>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <25 38 28 38 36 37 37 30>;
+ rates-mcs =
+ <1 20 28 32 31 34 22 27 28 29 27>,
+ <1 31 31 37 29 23 34 24 35 21 33>,
+ <1 28 37 38 36 23 27 28 28 24 26>,
+ <1 37 38 27 25 20 26 37 24 37 31>;
+ rates-ru =
+ <1 38 21 37 38 29 39 32 32 33 36 31 24>,
+ <1 32 38 34 32 23 28 38 33 24 25 24 35>,
+ <1 27 34 37 30 32 27 34 21 23 21 30 30>,
+ <1 25 38 25 37 30 31 23 35 35 22 38 25>,
+ <1 21 30 32 30 38 36 36 33 20 24 22 30>,
+ <1 29 36 29 31 34 20 31 39 26 28 23 39>,
+ <1 37 36 24 21 27 21 32 22 31 31 38 27>;
+ };
+ r6 {
+ channels = <12 12>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <21 25 26 32 30 25 37 30>;
+ rates-mcs =
+ <1 20 35 36 24 38 24 39 31 29 36>,
+ <1 28 35 26 32 25 35 35 38 36 35>,
+ <1 28 28 24 37 25 32 35 23 38 38>,
+ <1 22 22 24 26 37 33 38 37 37 39>;
+ rates-ru =
+ <1 20 34 22 32 29 23 33 35 24 31 28 22>,
+ <1 27 27 35 26 35 22 24 37 22 31 25 23>,
+ <1 28 23 29 26 36 27 32 27 23 27 36 31>,
+ <1 27 27 35 29 32 31 20 32 23 29 24 23>,
+ <1 39 27 37 30 25 34 20 23 29 22 32 22>,
+ <1 23 37 34 33 30 29 35 34 32 35 36 23>,
+ <1 22 29 30 33 39 27 30 34 22 34 39 36>;
+ };
+ r7 {
+ channels = <16 16>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <39 25 39 38 26 27 20 34>;
+ rates-mcs =
+ <1 29 30 27 31 35 24 36 27 36 21>,
+ <1 27 27 27 27 27 27 27 27 27 27>,
+ <1 27 33 35 38 20 30 38 24 23 23>,
+ <1 21 22 23 37 33 30 20 28 35 21>;
+ rates-ru =
+ <1 35 38 23 20 27 25 21 32 31 20 28 31>,
+ <1 26 21 30 22 36 32 38 23 31 25 25 38>,
+ <1 35 23 26 39 23 21 31 27 23 29 32 32>,
+ <1 22 36 35 26 21 29 30 32 20 20 23 36>,
+ <1 33 32 39 35 28 34 20 31 21 35 37 25>,
+ <1 27 22 28 28 30 36 38 31 33 28 31 39>,
+ <1 25 28 27 32 25 29 37 22 21 32 27 25>;
+ };
+ r8 {
+ channels = <36 36>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <36 36 36 36 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 37 37 35 35 33 33 30 30>,
+ <1 34 34 34 34 34 34 33 33 30 30>,
+ <1 33 33 33 33 33 33 33 33 30 30>,
+ <1 32 33 26 35 28 31 32 32 26 28>;
+ rates-ru =
+ <1 20 20 19 19 17 17 15 15 12 12 10 10>,
+ <1 26 26 25 25 23 23 21 21 18 18 16 16>,
+ <1 32 32 31 31 29 29 27 27 24 24 22 22>,
+ <1 38 38 37 37 35 35 33 33 30 30 28 28>,
+ <1 34 34 34 34 34 34 33 33 30 30 28 28>,
+ <2 33 33 33 33 33 33 33 33 30 30 28 28>;
+ };
+ r9 {
+ channels = <40 40>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <36 36 36 36 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 37 37 35 35 33 33 30 30>,
+ <1 34 34 34 34 34 34 33 33 30 30>,
+ <1 33 33 33 33 33 33 33 33 30 30>,
+ <1 25 23 21 23 38 25 26 39 20 34>;
+ rates-ru =
+ <1 20 20 19 19 17 17 15 15 12 12 10 10>,
+ <1 26 26 25 25 23 23 21 21 18 18 16 16>,
+ <1 32 32 31 31 29 29 27 27 24 24 22 22>,
+ <1 38 38 37 37 35 35 33 33 30 30 28 28>,
+ <1 34 34 34 34 34 34 33 33 30 30 28 28>,
+ <2 33 33 33 33 33 33 33 33 30 30 28 28>;
+ };
+ r10 {
+ channels = <44 44>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <36 36 36 36 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 37 37 35 35 33 33 30 30>,
+ <1 34 34 34 34 34 34 33 33 30 30>,
+ <1 33 33 33 33 33 33 33 33 30 30>,
+ <1 31 24 22 33 38 36 24 30 27 27>;
+ rates-ru =
+ <1 20 20 19 19 17 17 15 15 12 12 10 10>,
+ <1 26 26 25 25 23 23 21 21 18 18 16 16>,
+ <1 32 32 31 31 29 29 27 27 24 24 22 22>,
+ <1 38 38 37 37 35 35 33 33 30 30 28 28>,
+ <1 34 34 34 34 34 34 33 33 30 30 28 28>,
+ <2 33 33 33 33 33 33 33 33 30 30 28 28>;
+ };
+ r11 {
+ channels = <48 48>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <36 36 36 36 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 37 37 35 35 33 33 30 30>,
+ <1 34 34 34 34 34 34 33 33 30 30>,
+ <1 33 33 33 33 33 33 33 33 30 30>,
+ <1 32 24 25 39 21 30 32 39 36 26>;
+ rates-ru =
+ <1 20 20 19 19 17 17 15 15 12 12 10 10>,
+ <1 26 26 25 25 23 23 21 21 18 18 16 16>,
+ <1 32 32 31 31 29 29 27 27 24 24 22 22>,
+ <1 38 38 37 37 35 35 33 33 30 30 28 28>,
+ <1 34 34 34 34 34 34 33 33 30 30 28 28>,
+ <2 33 33 33 33 33 33 33 33 30 30 28 28>;
+ };
+ r12 {
+ channels = <52 52>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <39 39 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 42 42 38 38 35 35 33 33 30 30>,
+ <1 37 37 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 39 29 39 31 25 32 30 21 35 37>;
+ rates-ru =
+ <1 24 24 20 20 17 17 15 15 12 12 10 10>,
+ <1 30 30 26 26 23 23 21 21 18 18 16 16>,
+ <1 36 36 32 32 29 29 27 27 24 24 22 22>,
+ <1 42 42 38 38 35 35 33 33 30 30 28 28>,
+ <1 37 37 37 37 35 35 33 33 30 30 28 28>,
+ <2 36 36 36 36 35 35 33 33 30 30 28 28>;
+ };
+ r13 {
+ channels = <56 56>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <39 39 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 42 42 38 38 35 35 33 33 30 30>,
+ <1 37 37 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 37 31 37 36 33 38 32 36 24 33>;
+ rates-ru =
+ <1 24 24 20 20 17 17 15 15 12 12 10 10>,
+ <1 30 30 26 26 23 23 21 21 18 18 16 16>,
+ <1 36 36 32 32 29 29 27 27 24 24 22 22>,
+ <1 42 42 38 38 35 35 33 33 30 30 28 28>,
+ <1 37 37 37 37 35 35 33 33 30 30 28 28>,
+ <2 36 36 36 36 35 35 33 33 30 30 28 28>;
+ };
+ r14 {
+ channels = <60 60>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <39 39 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 42 42 38 38 35 35 33 33 30 30>,
+ <1 37 37 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 22 38 22 22 31 38 24 31 38 39>;
+ rates-ru =
+ <1 24 24 20 20 17 17 15 15 12 12 10 10>,
+ <1 30 30 26 26 23 23 21 21 18 18 16 16>,
+ <1 36 36 32 32 29 29 27 27 24 24 22 22>,
+ <1 42 42 38 38 35 35 33 33 30 30 28 28>,
+ <1 37 37 37 37 35 35 33 33 30 30 28 28>,
+ <2 36 36 36 36 35 35 33 33 30 30 28 28>;
+ };
+ r15 {
+ channels = <64 64>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <39 39 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 42 42 38 38 35 35 33 33 30 30>,
+ <1 37 37 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 23 23 37 36 29 38 33 36 24 25>;
+ rates-ru =
+ <1 24 24 20 20 17 17 15 15 12 12 10 10>,
+ <1 30 30 26 26 23 23 21 21 18 18 16 16>,
+ <1 36 36 32 32 29 29 27 27 24 24 22 22>,
+ <1 42 42 38 38 35 35 33 33 30 30 28 28>,
+ <1 37 37 37 37 35 35 33 33 30 30 28 28>,
+ <2 36 36 36 36 35 35 33 33 30 30 28 28>;
+ };
+ r16 {
+ channels = <68 68>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <39 39 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 42 42 38 38 35 35 33 33 30 30>,
+ <1 37 37 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 21 36 31 29 38 22 37 29 38 32>;
+ rates-ru =
+ <1 24 24 20 20 17 17 15 15 12 12 10 10>,
+ <1 30 30 26 26 23 23 21 21 18 18 16 16>,
+ <1 36 36 32 32 29 29 27 27 24 24 22 22>,
+ <1 42 42 38 38 35 35 33 33 30 30 28 28>,
+ <1 37 37 37 37 35 35 33 33 30 30 28 28>,
+ <2 36 36 36 36 35 35 33 33 30 30 28 28>;
+ };
+ r17 {
+ channels = <72 72>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <39 39 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 42 42 38 38 35 35 33 33 30 30>,
+ <1 37 37 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 33 33 38 22 32 32 31 20 32 28>;
+ rates-ru =
+ <1 24 24 20 20 17 17 15 15 12 12 10 10>,
+ <1 30 30 26 26 23 23 21 21 18 18 16 16>,
+ <1 36 36 32 32 29 29 27 27 24 24 22 22>,
+ <1 42 42 38 38 35 35 33 33 30 30 28 28>,
+ <1 37 37 37 37 35 35 33 33 30 30 28 28>,
+ <2 36 36 36 36 35 35 33 33 30 30 28 28>;
+ };
+ r18 {
+ channels = <76 76>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <39 39 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 42 42 38 38 35 35 33 33 30 30>,
+ <1 37 37 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 27 31 27 37 27 25 39 31 21 26>;
+ rates-ru =
+ <1 24 24 20 20 17 17 15 15 12 12 10 10>,
+ <1 30 30 26 26 23 23 21 21 18 18 16 16>,
+ <1 36 36 32 32 29 29 27 27 24 24 22 22>,
+ <1 42 42 38 38 35 35 33 33 30 30 28 28>,
+ <1 37 37 37 37 35 35 33 33 30 30 28 28>,
+ <2 36 36 36 36 35 35 33 33 30 30 28 28>;
+ };
+ r19 {
+ channels = <80 80>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <39 39 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 42 42 38 38 35 35 33 33 30 30>,
+ <1 37 37 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 21 26 31 25 20 39 31 34 34 22>;
+ rates-ru =
+ <1 24 24 20 20 17 17 15 15 12 12 10 10>,
+ <1 30 30 26 26 23 23 21 21 18 18 16 16>,
+ <1 36 36 32 32 29 29 27 27 24 24 22 22>,
+ <1 42 42 38 38 35 35 33 33 30 30 28 28>,
+ <1 37 37 37 37 35 35 33 33 30 30 28 28>,
+ <2 36 36 36 36 35 35 33 33 30 30 28 28>;
+ };
+ r20 {
+ channels = <84 84>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <39 39 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 42 42 38 38 35 35 33 33 30 30>,
+ <1 37 37 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 26 27 26 21 25 27 22 25 35 26>;
+ rates-ru =
+ <1 24 24 20 20 17 17 15 15 12 12 10 10>,
+ <1 30 30 26 26 23 23 21 21 18 18 16 16>,
+ <1 36 36 32 32 29 29 27 27 24 24 22 22>,
+ <1 42 42 38 38 35 35 33 33 30 30 28 28>,
+ <1 37 37 37 37 35 35 33 33 30 30 28 28>,
+ <2 36 36 36 36 35 35 33 33 30 30 28 28>;
+ };
+ r21 {
+ channels = <88 88>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <39 39 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 42 42 38 38 35 35 33 33 30 30>,
+ <1 37 37 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 20 37 35 30 28 29 36 38 32 25>;
+ rates-ru =
+ <1 24 24 20 20 17 17 15 15 12 12 10 10>,
+ <1 30 30 26 26 23 23 21 21 18 18 16 16>,
+ <1 36 36 32 32 29 29 27 27 24 24 22 22>,
+ <1 42 42 38 38 35 35 33 33 30 30 28 28>,
+ <1 37 37 37 37 35 35 33 33 30 30 28 28>,
+ <2 36 36 36 36 35 35 33 33 30 30 28 28>;
+ };
+ r22 {
+ channels = <92 92>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <39 39 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 42 42 38 38 35 35 33 33 30 30>,
+ <1 37 37 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 30 37 37 20 22 34 23 26 21 35>;
+ rates-ru =
+ <1 24 24 20 20 17 17 15 15 12 12 10 10>,
+ <1 30 30 26 26 23 23 21 21 18 18 16 16>,
+ <1 36 36 32 32 29 29 27 27 24 24 22 22>,
+ <1 42 42 38 38 35 35 33 33 30 30 28 28>,
+ <1 37 37 37 37 35 35 33 33 30 30 28 28>,
+ <2 36 36 36 36 35 35 33 33 30 30 28 28>;
+ };
+ r23 {
+ channels = <96 96>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <39 39 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 42 42 38 38 35 35 33 33 30 30>,
+ <1 37 37 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 24 28 27 23 32 23 20 26 20 32>;
+ rates-ru =
+ <1 24 24 20 20 17 17 15 15 12 12 10 10>,
+ <1 30 30 26 26 23 23 21 21 18 18 16 16>,
+ <1 36 36 32 32 29 29 27 27 24 24 22 22>,
+ <1 42 42 38 38 35 35 33 33 30 30 28 28>,
+ <1 37 37 37 37 35 35 33 33 30 30 28 28>,
+ <2 36 36 36 36 35 35 33 33 30 30 28 28>;
+ };
+ r24 {
+ channels = <100 100>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <41 41 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 40 40 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 30 27 25 39 31 35 28 37 27 28>;
+ rates-ru =
+ <1 22 22 19 19 17 17 15 15 12 12 10 10>,
+ <1 28 28 25 25 23 23 21 21 18 18 16 16>,
+ <1 34 34 31 31 29 29 27 27 24 24 22 22>,
+ <1 40 40 37 37 35 35 33 33 30 30 28 28>,
+ <1 36 36 36 36 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r25 {
+ channels = <104 104>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <41 41 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 40 40 37 37 35 35 33 33 30 30>,
+ <1 36 36 36 36 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 24 22 26 38 28 24 34 38 32 37>;
+ rates-ru =
+ <1 22 22 19 19 17 17 15 15 12 12 10 10>,
+ <1 28 28 25 25 23 23 21 21 18 18 16 16>,
+ <1 34 34 31 31 29 29 27 27 24 24 22 22>,
+ <1 40 40 37 37 35 35 33 33 30 30 28 28>,
+ <1 36 36 36 36 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r26 {
+ channels = <108 108>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <41 41 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 40 40 37 37 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 25 26 21 34 38 38 31 23 36 38>;
+ rates-ru =
+ <1 22 22 19 19 17 17 15 15 12 12 10 10>,
+ <1 28 28 25 25 23 23 21 21 18 18 16 16>,
+ <1 34 34 31 31 29 29 27 27 24 24 22 22>,
+ <1 40 40 37 37 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r27 {
+ channels = <112 112>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <41 41 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 40 40 37 37 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 38 38 28 26 21 39 35 26 35 21>;
+ rates-ru =
+ <1 22 22 19 19 17 17 15 15 12 12 10 10>,
+ <1 28 28 25 25 23 23 21 21 18 18 16 16>,
+ <1 34 34 31 31 29 29 27 27 24 24 22 22>,
+ <1 40 40 37 37 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r28 {
+ channels = <116 116>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <41 41 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 40 40 37 37 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 21 20 22 39 36 21 31 39 36 39>;
+ rates-ru =
+ <1 22 22 19 19 17 17 15 15 12 12 10 10>,
+ <1 28 28 25 25 23 23 21 21 18 18 16 16>,
+ <1 34 34 31 31 29 29 27 27 24 24 22 22>,
+ <1 40 40 37 37 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r29 {
+ channels = <120 120>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <41 41 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 40 40 37 37 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 39 21 34 39 28 25 28 26 26 36>;
+ rates-ru =
+ <1 22 22 19 19 17 17 15 15 12 12 10 10>,
+ <1 28 28 25 25 23 23 21 21 18 18 16 16>,
+ <1 34 34 31 31 29 29 27 27 24 24 22 22>,
+ <1 40 40 37 37 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r30 {
+ channels = <124 124>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <41 41 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 40 40 37 37 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 22 34 36 32 32 21 29 28 29 21>;
+ rates-ru =
+ <1 22 22 19 19 17 17 15 15 12 12 10 10>,
+ <1 28 28 25 25 23 23 21 21 18 18 16 16>,
+ <1 34 34 31 31 29 29 27 27 24 24 22 22>,
+ <1 40 40 37 37 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r31 {
+ channels = <128 128>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <41 41 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 40 40 37 37 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 29 20 37 33 26 39 32 35 27 27>;
+ rates-ru =
+ <1 22 22 19 19 17 17 15 15 12 12 10 10>,
+ <1 28 28 25 25 23 23 21 21 18 18 16 16>,
+ <1 34 34 31 31 29 29 27 27 24 24 22 22>,
+ <1 40 40 37 37 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r32 {
+ channels = <132 132>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <41 41 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 40 40 37 37 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 30 27 24 30 27 24 35 31 38 39>;
+ rates-ru =
+ <1 22 22 19 19 17 17 15 15 12 12 10 10>,
+ <1 28 28 25 25 23 23 21 21 18 18 16 16>,
+ <1 34 34 31 31 29 29 27 27 24 24 22 22>,
+ <1 40 40 37 37 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r33 {
+ channels = <136 136>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <41 41 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 40 40 37 37 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 36 37 38 34 22 33 32 23 24 37>;
+ rates-ru =
+ <1 22 22 19 19 17 17 15 15 12 12 10 10>,
+ <1 28 28 25 25 23 23 21 21 18 18 16 16>,
+ <1 34 34 31 31 29 29 27 27 24 24 22 22>,
+ <1 40 40 37 37 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r34 {
+ channels = <140 140>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <37 37 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 36 36 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 32 29 37 27 27 25 21 31 35 20>;
+ rates-ru =
+ <1 20 20 18 18 17 17 15 15 12 12 10 10>,
+ <1 26 26 24 24 23 23 21 21 18 18 16 16>,
+ <1 32 32 30 30 29 29 27 27 24 24 22 22>,
+ <1 38 38 36 36 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r35 {
+ channels = <144 144>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <37 37 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 36 36 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 38 39 29 38 29 22 33 35 38 28>;
+ rates-ru =
+ <1 20 20 18 18 17 17 15 15 12 12 10 10>,
+ <1 26 26 24 24 23 23 21 21 18 18 16 16>,
+ <1 32 32 30 30 29 29 27 27 24 24 22 22>,
+ <1 38 38 36 36 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r36 {
+ channels = <149 149>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <37 37 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 36 36 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 25 25 30 32 37 31 24 29 38 21>;
+ rates-ru =
+ <1 20 20 18 18 17 17 15 15 12 12 10 10>,
+ <1 26 26 24 24 23 23 21 21 18 18 16 16>,
+ <1 32 32 30 30 29 29 27 27 24 24 22 22>,
+ <1 38 38 36 36 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r37 {
+ channels = <153 153>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <37 37 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 36 36 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 27 25 34 27 36 30 26 36 21 34>;
+ rates-ru =
+ <1 20 20 18 18 17 17 15 15 12 12 10 10>,
+ <1 26 26 24 24 23 23 21 21 18 18 16 16>,
+ <1 32 32 30 30 29 29 27 27 24 24 22 22>,
+ <1 38 38 36 36 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r38 {
+ channels = <157 157>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <37 37 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 36 36 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 30 32 21 22 25 28 34 39 23 36>;
+ rates-ru =
+ <1 20 20 18 18 17 17 15 15 12 12 10 10>,
+ <1 26 26 24 24 23 23 21 21 18 18 16 16>,
+ <1 32 32 30 30 29 29 27 27 24 24 22 22>,
+ <1 38 38 36 36 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r39 {
+ channels = <161 161>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <37 37 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 36 36 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 26 23 35 27 38 27 21 34 39 27>;
+ rates-ru =
+ <1 20 20 18 18 17 17 15 15 12 12 10 10>,
+ <1 26 26 24 24 23 23 21 21 18 18 16 16>,
+ <1 32 32 30 30 29 29 27 27 24 24 22 22>,
+ <1 38 38 36 36 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r40 {
+ channels = <165 165>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <37 37 38 38 36 36 34 34>;
+ rates-mcs =
+ <1 38 38 36 36 35 35 33 33 30 30>,
+ <1 40 40 38 38 35 35 33 33 30 30>,
+ <1 35 35 35 35 35 35 33 33 30 30>,
+ <1 21 24 20 31 28 31 20 21 29 27>;
+ rates-ru =
+ <1 20 20 18 18 17 17 15 15 12 12 10 10>,
+ <1 26 26 24 24 23 23 21 21 18 18 16 16>,
+ <1 32 32 30 30 29 29 27 27 24 24 22 22>,
+ <1 38 38 36 36 35 35 33 33 30 30 28 28>,
+ <1 40 40 38 38 35 35 33 33 30 30 28 28>,
+ <2 35 35 35 35 35 35 33 33 30 30 28 28>;
+ };
+ r41 {
+ channels = <169 169>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <36 31 21 37 27 38 38 37>;
+ rates-mcs =
+ <1 35 37 34 32 25 25 24 27 21 29>,
+ <1 34 33 36 26 38 38 37 34 25 29>,
+ <1 33 35 21 22 39 24 32 33 37 38>,
+ <1 34 28 30 26 22 37 29 29 31 26>;
+ rates-ru =
+ <1 25 25 37 23 29 39 37 26 27 20 39 29>,
+ <1 39 37 39 32 36 27 32 38 33 27 33 24>,
+ <1 21 27 35 35 37 39 26 33 29 21 27 36>,
+ <1 29 27 26 24 38 32 21 38 27 30 32 25>,
+ <1 21 22 36 33 28 32 31 24 35 22 22 20>,
+ <1 39 34 24 21 36 30 33 33 29 35 36 26>,
+ <1 28 38 34 27 26 33 35 28 28 25 29 24>;
+ };
+ r42 {
+ channels = <173 173>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <23 32 34 39 26 33 22 30>;
+ rates-mcs =
+ <1 22 25 22 25 28 21 20 24 30 39>,
+ <1 26 30 32 35 32 37 21 38 36 30>,
+ <1 35 33 27 24 37 24 28 29 21 32>,
+ <1 31 24 29 23 38 30 34 31 38 20>;
+ rates-ru =
+ <1 38 24 39 20 36 25 39 26 33 35 25 38>,
+ <1 29 26 31 33 39 37 36 39 20 26 36 21>,
+ <1 24 27 22 30 33 31 33 23 32 29 35 28>,
+ <1 34 33 25 25 35 37 22 31 20 20 27 35>,
+ <1 22 28 35 27 20 26 25 39 20 25 37 21>,
+ <1 35 35 28 23 27 20 29 25 31 33 20 38>,
+ <1 25 29 31 24 30 35 36 32 34 31 37 30>;
+ };
+ r43 {
+ channels = <177 177>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <26 20 32 34 37 35 39 31>;
+ rates-mcs =
+ <1 28 20 39 30 31 22 30 39 21 22>,
+ <1 34 38 35 25 38 33 34 23 38 34>,
+ <1 34 32 34 25 29 24 32 29 22 36>,
+ <1 20 26 36 37 38 24 29 39 39 27>;
+ rates-ru =
+ <1 28 35 34 20 22 22 27 22 28 33 23 38>,
+ <1 22 21 27 26 36 31 39 32 25 21 37 23>,
+ <1 25 30 37 28 39 32 30 26 24 25 22 34>,
+ <1 30 20 33 35 20 34 24 22 38 31 24 21>,
+ <1 31 22 24 26 27 23 33 24 27 35 32 28>,
+ <1 25 34 33 27 34 31 33 20 38 31 24 23>,
+ <1 27 30 28 36 33 33 21 36 36 33 34 20>;
+ };
+ r44 {
+ channels = <181 181>;
+ txs_delta = <0 0 0>;
+ rates-ofdm = <36 30 37 33 32 30 20 38>;
+ rates-mcs =
+ <1 20 26 22 38 26 36 28 24 29 31>,
+ <1 20 26 29 35 38 31 33 21 37 29>,
+ <1 39 30 24 35 22 31 30 37 23 37>,
+ <1 38 21 30 37 24 34 29 29 23 26>;
+ rates-ru =
+ <1 36 24 21 23 39 28 21 36 38 30 24 33>,
+ <1 38 24 29 37 30 23 29 35 23 33 39 30>,
+ <1 31 33 26 38 32 29 21 30 22 28 30 20>,
+ <1 30 32 27 33 38 24 30 31 25 22 20 21>,
+ <1 34 38 37 24 33 35 33 31 22 28 21 31>,
+ <1 38 29 34 28 26 23 37 39 34 37 22 36>,
+ <1 36 23 21 24 25 25 20 35 33 24 24 22>;
+ };
};
};
};
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0>;
- enable-method = "psci";
- clock-frequency = <80000000>;
- next-level-cache = <&L2_0>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x1>;
- enable-method = "psci";
- clock-frequency = <80000000>;
- next-level-cache = <&L2_0>;
- };
-
- L2_0: l2-cache0 {
- compatible = "cache";
- };
};
- gic: interrupt-controller@09000000 {
- compatible = "arm,gic-v3";
+ pcie_intc0: interrupt-controller {
interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x09000000 0x20000>,
- <0x09080000 0x80000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
-
- its: gic-its@09020000 {
- compatible = "arm,gic-v3-its";
- msi-controller;
- #msi-cell = <1>;
- reg = <0x090200000 0x20000>;
- };
- };
-
-
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- clock-frequency = <25000000>;
- };
-
- pmu {
- //compatible = "arm,armv8-pmuv3";
- compatible = "arm,cortex-a15-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- npu@1e800000 {
- compatible = "econet,ecnt-npu";
- reg = <0x1e800000 0x60000>, //NPU 384K SRAM
- <0x1e900000 0x313000>; //NPU 16K SRAM, Registers
- memory-region = <&npu_reserved>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 102+16 tr done
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 105+16 hadap irq0
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; //mbox2host irq
- };
-
- apb_timer1: apb_timer1@1fbf0100 {
- compatible = "econet,ecnt-timer";
- reg = <0x1fbf0100 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x40000000>;
- };
-
- rbus@1fa00000 {
- compatible = "econet,ecnt-rbus";
- reg = <0x1fa00000 0x1000>; //RBus Core
- };
-
- sram@1fa40000 {
- compatible = "econet,ecnt-sram";
- reg = <0x1fa40000 0x8000>, //GDMP SRAM
- <0x08000000 0x40000>, //L2C SRAM (only for CPU internal access)
- <0x1EFC0000 0x40000>, //L2C SRAM (only for CPU/NPU/GDMA/SPI/Crypto/WOE external access via pbus)
- <0x1E880000 0x40000>, //L2C SRAM (only for CPU/NPU/HSDMA/PCIE external access via npu_rbus)
- <0x1fbe3000 0x200>; //I2C_SLAVE SRAM
- };
-
- scu@1fb00000 {
- compatible = "econet,ecnt-scu";
- reg = <0x1fb00000 0x960>, //NP SCU
- <0x1fa20000 0x360>, //CHIP SCU
- <0x1fa2FF30 0x10>; //Rbus clk ctl for FPGA
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pcie@0x1fa91000 {
- compatible = "ecnt,pcie-en7523";
- device_type = "pci";
- reg = <0x1fa91000 0x1000>,
- <0x1fa92000 0x1000>,
- <0x1fa90000 0x1000>, /* pcie top*/
- <0x1a100000 0x1000>, /* switch lane */
- <0x1a148000 0x1000>, /* 4, rc0 phy base, for change xtal setting */
- <0x1a14a000 0x1000>; /* 5, rc1 phy base, for change xtal setting */
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, //23+16
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; //24+16
- bus-range = <0x00 0xff>;
- #address-cells = <3>;
- #size-cells = <2>;
- /* change xtal for 40M, default is 25M */
- /* change-xtal; */
- /* disable io coherent for RC and EP default. */
- /*dma-coherent;*/
- ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
-
- pcie0: pcie@0,0 {
- device_type = "pci";
- reg = <0x0000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc0 1>,
- <0 0 0 2 &pcie_intc0 2>,
- <0 0 0 3 &pcie_intc0 3>,
- <0 0 0 4 &pcie_intc0 4>;
- pcie-port = <0>;
- num-lanes = <1>;
- status = "okay";
-
- mt7915@0,0{
- reg = <0x0000 0 0 0 0>;
- power-limits{
- r0{
- regdomain = "etsi";
- txpower-2g {
- r1 {
- channels = <1 1>;
- txs_delta = <0 0 0>;
- rates-cck = <30 30 30 30>;
- rates-ofdm = <38 38 38 38 36 36 34 34>;
- rates-mcs =
- <1 38 38 36 36 34 34 32 32 30 30>,
- <1 37 37 36 36 34 34 32 32 30 30>,
- <1 30 31 32 30 20 33 25 23 39 34>,
- <1 24 26 36 28 31 33 23 33 21 25>;
- rates-ru =
- <1 20 20 18 18 16 16 14 14 12 12 10 10>,
- <1 26 26 24 24 22 22 20 20 18 18 16 16>,
- <1 32 32 30 30 28 28 26 26 24 24 22 22>,
- <1 38 38 36 36 34 34 32 32 30 30 28 28>,
- <1 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 23 34 23 35 38 24 26 38 28 29 24 34>,
- <1 33 37 27 27 33 35 22 24 37 28 27 26>;
-
- };
- r2 {
- channels = <2 2>;
- txs_delta = <0 0 0>;
- rates-cck = <30 30 30 30>;
- rates-ofdm = <38 38 38 38 36 36 34 34>;
- rates-mcs =
- <1 38 38 36 36 34 34 32 32 30 30>,
- <1 37 37 36 36 34 34 32 32 30 30>,
- <1 29 26 37 20 35 27 31 23 27 23>,
- <1 28 33 25 28 27 23 24 33 24 21>;
- rates-ru =
- <1 20 20 18 18 16 16 14 14 12 12 10 10>,
- <1 26 26 24 24 22 22 20 20 18 18 16 16>,
- <1 32 32 30 30 28 28 26 26 24 24 22 22>,
- <1 38 38 36 36 34 34 32 32 30 30 28 28>,
- <1 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 28 22 29 39 21 39 29 24 23 32 25 21>,
- <1 23 32 30 39 29 27 36 26 22 33 34 29>;
-
- };
- r3 {
- channels = <3 3>;
- txs_delta = <0 0 0>;
- rates-cck = <31 31 31 31>;
- rates-ofdm = <38 38 38 38 36 36 34 34>;
- rates-mcs =
- <1 38 38 36 36 34 34 32 32 30 30>,
- <1 37 37 36 36 34 34 32 32 30 30>,
- <1 38 24 33 22 26 36 31 23 39 33>,
- <1 33 34 34 35 22 28 21 35 35 33>;
- rates-ru =
- <1 20 20 18 18 16 16 14 14 12 12 10 10>,
- <1 26 26 24 24 22 22 20 20 18 18 16 16>,
- <1 32 32 30 30 28 28 26 26 24 24 22 22>,
- <1 38 38 36 36 34 34 32 32 30 30 28 28>,
- <1 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 38 34 33 32 37 30 28 22 36 28 31 30>,
- <1 20 25 31 29 23 24 24 39 20 27 29 20>;
-
- };
- r4 {
- channels = <4 4>;
- txs_delta = <0 0 0>;
- rates-cck = <31 31 31 31>;
- rates-ofdm = <38 38 38 38 36 36 34 34>;
- rates-mcs =
- <1 38 38 36 36 34 34 32 32 30 30>,
- <1 37 37 36 36 34 34 32 32 30 30>,
- <1 38 23 25 21 27 38 20 23 39 36>,
- <1 23 24 20 26 37 31 29 30 22 36>;
- rates-ru =
- <1 20 20 18 18 16 16 14 14 12 12 10 10>,
- <1 26 26 24 24 22 22 20 20 18 18 16 16>,
- <1 32 32 30 30 28 28 26 26 24 24 22 22>,
- <1 38 38 36 36 34 34 32 32 30 30 28 28>,
- <1 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 37 34 38 35 35 39 38 26 39 37 24 34>,
- <1 29 31 24 39 24 22 20 28 34 31 30 21>;
-
- };
- r5 {
- channels = <5 5>;
- txs_delta = <0 0 0>;
- rates-cck = <31 31 31 31>;
- rates-ofdm = <38 38 38 38 36 36 34 34>;
- rates-mcs =
- <1 38 38 36 36 34 34 32 32 30 30>,
- <1 37 37 36 36 34 34 32 32 30 30>,
- <1 21 37 28 38 39 35 30 29 36 24>,
- <1 30 22 37 34 37 32 34 27 27 31>;
- rates-ru =
- <1 20 20 18 18 16 16 14 14 12 12 10 10>,
- <1 26 26 24 24 22 22 20 20 18 18 16 16>,
- <1 32 32 30 30 28 28 26 26 24 24 22 22>,
- <1 38 38 36 36 34 34 32 32 30 30 28 28>,
- <1 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 38 33 36 39 24 24 24 36 29 37 21 29>,
- <1 20 36 39 30 25 33 39 25 36 22 22 26>;
-
- };
- r6 {
- channels = <6 6>;
- txs_delta = <0 0 0>;
- rates-cck = <31 31 31 31>;
- rates-ofdm = <37 37 37 37 36 36 34 34>;
- rates-mcs =
- <2 37 37 36 36 34 34 32 32 30 30>,
- <1 33 39 30 36 33 37 38 39 38 35>,
- <1 29 23 22 36 23 21 28 35 36 33>;
- rates-ru =
- <1 19 19 18 18 16 16 14 14 12 12 10 10>,
- <1 25 25 24 24 22 22 20 20 18 18 16 16>,
- <1 31 31 30 30 28 28 26 26 24 24 22 22>,
- <2 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 23 23 31 30 21 30 27 33 27 23 31 23>,
- <1 39 36 25 24 38 36 24 30 29 39 21 22>;
-
- };
- r7 {
- channels = <7 7>;
- txs_delta = <0 0 0>;
- rates-cck = <31 31 31 31>;
- rates-ofdm = <37 37 37 37 36 36 34 34>;
- rates-mcs =
- <2 37 37 36 36 34 34 32 32 30 30>,
- <1 22 29 34 29 20 28 37 32 28 38>,
- <1 31 23 31 36 25 21 23 23 23 36>;
- rates-ru =
- <1 19 19 18 18 16 16 14 14 12 12 10 10>,
- <1 25 25 24 24 22 22 20 20 18 18 16 16>,
- <1 31 31 30 30 28 28 26 26 24 24 22 22>,
- <2 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 34 24 28 32 24 39 21 39 25 39 34 21>,
- <1 33 24 24 24 28 31 39 36 31 23 20 25>;
-
- };
- r8 {
- channels = <8 8>;
- txs_delta = <0 0 0>;
- rates-cck = <31 31 31 31>;
- rates-ofdm = <37 37 37 37 36 36 34 34>;
- rates-mcs =
- <2 37 37 36 36 34 34 32 32 30 30>,
- <1 27 20 34 28 20 20 30 36 31 35>,
- <1 37 20 34 38 35 28 20 32 21 25>;
- rates-ru =
- <1 19 19 18 18 16 16 14 14 12 12 10 10>,
- <1 25 25 24 24 22 22 20 20 18 18 16 16>,
- <1 31 31 30 30 28 28 26 26 24 24 22 22>,
- <2 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 21 28 28 37 39 27 21 36 29 24 28 32>,
- <1 26 27 22 28 32 20 30 26 29 28 31 38>;
-
- };
- r9 {
- channels = <9 9>;
- txs_delta = <0 0 0>;
- rates-cck = <31 31 31 31>;
- rates-ofdm = <37 37 37 37 36 36 34 34>;
- rates-mcs =
- <2 37 37 36 36 34 34 32 32 30 30>,
- <1 25 25 27 35 32 35 20 30 32 37>,
- <1 36 34 38 30 35 39 36 33 20 25>;
- rates-ru =
- <1 19 19 18 18 16 16 14 14 12 12 10 10>,
- <1 25 25 24 24 22 22 20 20 18 18 16 16>,
- <1 31 31 30 30 28 28 26 26 24 24 22 22>,
- <2 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 37 22 30 38 26 27 28 23 28 31 26 39>,
- <1 22 39 29 24 39 35 34 37 38 36 29 27>;
-
- };
- r10 {
- channels = <10 10>;
- txs_delta = <0 0 0>;
- rates-cck = <31 31 31 31>;
- rates-ofdm = <37 37 37 37 36 36 34 34>;
- rates-mcs =
- <2 37 37 36 36 34 34 32 32 30 30>,
- <1 31 39 34 29 38 29 38 35 24 20>,
- <1 36 34 25 32 32 28 39 25 35 24>;
- rates-ru =
- <1 19 19 18 18 16 16 14 14 12 12 10 10>,
- <1 25 25 24 24 22 22 20 20 18 18 16 16>,
- <1 31 31 30 30 28 28 26 26 24 24 22 22>,
- <2 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 36 31 30 32 20 24 39 25 36 29 22 28>,
- <1 32 28 37 35 24 25 20 38 35 33 29 27>;
-
- };
- r11 {
- channels = <11 11>;
- txs_delta = <0 0 0>;
- rates-cck = <31 31 31 31>;
- rates-ofdm = <37 37 37 37 36 36 34 34>;
- rates-mcs =
- <1 37 37 36 36 34 34 32 32 30 30>,
- <1 36 36 36 36 34 34 32 32 30 30>,
- <1 23 26 33 31 26 21 38 34 39 20>,
- <1 29 30 22 31 34 33 28 34 24 20>;
- rates-ru =
- <1 19 19 18 18 16 16 14 14 12 12 10 10>,
- <1 25 25 24 24 22 22 20 20 18 18 16 16>,
- <1 31 31 30 30 28 28 26 26 24 24 22 22>,
- <1 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 36 36 36 36 34 34 32 32 30 30 28 28>,
- <1 29 24 30 33 37 39 36 36 29 36 24 26>,
- <1 25 28 33 34 34 23 22 36 33 35 22 24>;
-
- };
- r12 {
- channels = <12 12>;
- txs_delta = <0 0 0>;
- rates-cck = <31 31 31 31>;
- rates-ofdm = <37 37 37 37 36 36 34 34>;
- rates-mcs =
- <1 37 37 36 36 34 34 32 32 30 30>,
- <1 36 36 36 36 34 34 32 32 30 30>,
- <1 20 36 37 24 24 29 34 27 31 24>,
- <1 29 22 21 38 24 25 31 23 20 21>;
- rates-ru =
- <1 19 19 18 18 16 16 14 14 12 12 10 10>,
- <1 25 25 24 24 22 22 20 20 18 18 16 16>,
- <1 31 31 30 30 28 28 26 26 24 24 22 22>,
- <1 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 36 36 36 36 34 34 32 32 30 30 28 28>,
- <1 31 26 23 24 36 34 24 30 24 25 31 24>,
- <1 35 23 20 39 28 25 24 30 34 33 32 32>;
-
- };
- r13 {
- channels = <13 13>;
- txs_delta = <0 0 0>;
- rates-cck = <31 31 31 31>;
- rates-ofdm = <37 37 37 37 36 36 34 34>;
- rates-mcs =
- <1 37 37 36 36 34 34 32 32 30 30>,
- <1 36 36 36 36 34 34 32 32 30 30>,
- <1 29 24 37 23 38 36 39 32 35 33>,
- <1 21 26 33 29 27 28 34 36 23 32>;
- rates-ru =
- <1 19 19 18 18 16 16 14 14 12 12 10 10>,
- <1 25 25 24 24 22 22 20 20 18 18 16 16>,
- <1 31 31 30 30 28 28 26 26 24 24 22 22>,
- <1 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 36 36 36 36 34 34 32 32 30 30 28 28>,
- <1 34 34 36 28 28 35 30 34 24 32 27 36>,
- <1 34 30 24 34 36 36 20 23 25 31 31 20>;
-
- };
- r14 {
- channels = <14 14>;
- txs_delta = <0 0 0>;
- rates-cck = <31 31 31 31>;
- rates-ofdm = <37 37 37 37 36 36 34 34>;
- rates-mcs =
- <1 37 37 36 36 34 34 32 32 30 30>,
- <1 36 36 36 36 34 34 32 32 30 30>,
- <1 38 29 37 27 28 24 32 37 33 22>,
- <1 31 37 23 28 23 35 21 22 20 34>;
- rates-ru =
- <1 19 19 18 18 16 16 14 14 12 12 10 10>,
- <1 25 25 24 24 22 22 20 20 18 18 16 16>,
- <1 31 31 30 30 28 28 26 26 24 24 22 22>,
- <1 37 37 36 36 34 34 32 32 30 30 28 28>,
- <1 36 36 36 36 34 34 32 32 30 30 28 28>,
- <1 30 28 21 29 34 23 32 31 24 26 36 30>,
- <1 22 28 32 29 24 20 23 21 33 33 22 24>;
-
- };
- };
- txpower-5g {
- r1 {
- channels = <184 184>;
- txs_delta = <0 0 0>;
- rates-ofdm = <36 30 24 34 24 21 25 37>;
- rates-mcs =
- <1 26 39 32 20 39 32 30 22 38 36>,
- <1 25 26 30 26 28 21 31 22 31 22>,
- <1 35 22 33 26 22 25 21 38 23 30>,
- <1 34 29 20 37 33 32 39 30 26 22>;
- rates-ru =
- <1 27 28 21 34 34 33 25 23 36 39 27 31>,
- <1 33 20 24 26 32 29 36 23 35 29 31 21>,
- <1 21 33 34 29 23 26 22 20 29 28 36 23>,
- <1 20 29 38 21 22 23 36 20 26 27 22 23>,
- <1 28 38 24 25 30 25 34 39 23 21 36 26>,
- <1 38 32 21 35 22 21 36 32 29 28 20 20>,
- <1 26 38 39 27 34 38 29 39 30 26 26 36>;
-
- };
- r2 {
- channels = <188 188>;
- txs_delta = <0 0 0>;
- rates-ofdm = <29 33 22 28 39 35 24 32>;
- rates-mcs =
- <1 39 33 38 34 26 35 28 38 33 31>,
- <1 38 20 22 24 35 24 37 28 37 28>,
- <1 31 23 26 28 21 33 37 35 32 31>,
- <1 22 23 26 22 24 38 25 20 27 31>;
- rates-ru =
- <1 32 39 28 30 26 25 20 35 27 36 28 24>,
- <1 37 32 35 34 34 21 20 28 39 35 20 28>,
- <1 25 22 32 37 31 26 36 30 29 29 38 32>,
- <1 29 24 39 29 34 29 27 31 27 39 26 39>,
- <1 32 32 20 25 37 20 32 34 26 24 37 37>,
- <1 32 25 20 21 34 36 34 39 23 37 31 35>,
- <1 24 28 36 21 23 22 25 33 33 24 30 22>;
-
- };
- r3 {
- channels = <192 192>;
- txs_delta = <0 0 0>;
- rates-ofdm = <34 33 23 36 22 22 29 38>;
- rates-mcs =
- <1 35 30 20 26 36 37 38 23 24 20>,
- <1 24 22 31 32 32 36 33 30 27 30>,
- <1 22 26 22 34 22 30 28 34 38 22>,
- <1 33 35 23 22 31 37 35 37 23 36>;
- rates-ru =
- <1 24 23 24 21 23 29 37 32 20 37 36 29>,
- <1 39 20 22 26 34 21 33 31 39 23 38 22>,
- <1 38 33 27 37 26 39 22 27 20 27 37 39>,
- <1 35 37 33 31 31 39 35 31 38 33 36 31>,
- <1 21 32 32 25 32 34 39 37 27 25 39 29>,
- <1 35 31 21 30 32 39 38 37 29 22 28 22>,
- <1 38 38 27 38 20 22 38 22 22 34 30 28>;
-
- };
- r4 {
- channels = <196 196>;
- txs_delta = <0 0 0>;
- rates-ofdm = <22 32 38 39 35 25 21 23>;
- rates-mcs =
- <1 35 38 34 21 30 25 32 23 29 37>,
- <1 29 33 24 23 28 33 23 30 24 34>,
- <1 28 23 21 33 39 38 39 27 38 22>,
- <1 30 24 36 21 26 38 32 30 37 30>;
- rates-ru =
- <1 20 34 37 34 39 34 25 34 20 31 33 22>,
- <1 27 34 33 30 24 24 22 29 37 35 34 26>,
- <1 36 37 36 37 37 32 34 27 35 33 23 21>,
- <1 24 29 28 20 27 34 28 29 35 24 36 39>,
- <1 39 33 28 23 34 39 34 39 25 38 35 29>,
- <1 25 32 32 20 29 37 27 22 37 26 29 33>,
- <1 33 23 35 38 31 29 29 22 36 35 33 25>;
-
- };
- r5 {
- channels = <8 8>;
- txs_delta = <0 0 0>;
- rates-ofdm = <25 38 28 38 36 37 37 30>;
- rates-mcs =
- <1 20 28 32 31 34 22 27 28 29 27>,
- <1 31 31 37 29 23 34 24 35 21 33>,
- <1 28 37 38 36 23 27 28 28 24 26>,
- <1 37 38 27 25 20 26 37 24 37 31>;
- rates-ru =
- <1 38 21 37 38 29 39 32 32 33 36 31 24>,
- <1 32 38 34 32 23 28 38 33 24 25 24 35>,
- <1 27 34 37 30 32 27 34 21 23 21 30 30>,
- <1 25 38 25 37 30 31 23 35 35 22 38 25>,
- <1 21 30 32 30 38 36 36 33 20 24 22 30>,
- <1 29 36 29 31 34 20 31 39 26 28 23 39>,
- <1 37 36 24 21 27 21 32 22 31 31 38 27>;
-
- };
- r6 {
- channels = <12 12>;
- txs_delta = <0 0 0>;
- rates-ofdm = <21 25 26 32 30 25 37 30>;
- rates-mcs =
- <1 20 35 36 24 38 24 39 31 29 36>,
- <1 28 35 26 32 25 35 35 38 36 35>,
- <1 28 28 24 37 25 32 35 23 38 38>,
- <1 22 22 24 26 37 33 38 37 37 39>;
- rates-ru =
- <1 20 34 22 32 29 23 33 35 24 31 28 22>,
- <1 27 27 35 26 35 22 24 37 22 31 25 23>,
- <1 28 23 29 26 36 27 32 27 23 27 36 31>,
- <1 27 27 35 29 32 31 20 32 23 29 24 23>,
- <1 39 27 37 30 25 34 20 23 29 22 32 22>,
- <1 23 37 34 33 30 29 35 34 32 35 36 23>,
- <1 22 29 30 33 39 27 30 34 22 34 39 36>;
-
- };
- r7 {
- channels = <16 16>;
- txs_delta = <0 0 0>;
- rates-ofdm = <39 25 39 38 26 27 20 34>;
- rates-mcs =
- <1 29 30 27 31 35 24 36 27 36 21>,
- <1 27 27 27 27 27 27 27 27 27 27>,
- <1 27 33 35 38 20 30 38 24 23 23>,
- <1 21 22 23 37 33 30 20 28 35 21>;
- rates-ru =
- <1 35 38 23 20 27 25 21 32 31 20 28 31>,
- <1 26 21 30 22 36 32 38 23 31 25 25 38>,
- <1 35 23 26 39 23 21 31 27 23 29 32 32>,
- <1 22 36 35 26 21 29 30 32 20 20 23 36>,
- <1 33 32 39 35 28 34 20 31 21 35 37 25>,
- <1 27 22 28 28 30 36 38 31 33 28 31 39>,
- <1 25 28 27 32 25 29 37 22 21 32 27 25>;
-
- };
- r8 {
- channels = <36 36>;
- txs_delta = <0 0 0>;
- rates-ofdm = <36 36 36 36 36 36 34 34>;
- rates-mcs =
- <1 38 38 37 37 35 35 33 33 30 30>,
- <1 34 34 34 34 34 34 33 33 30 30>,
- <1 33 33 33 33 33 33 33 33 30 30>,
- <1 32 33 26 35 28 31 32 32 26 28>;
- rates-ru =
- <1 20 20 19 19 17 17 15 15 12 12 10 10>,
- <1 26 26 25 25 23 23 21 21 18 18 16 16>,
- <1 32 32 31 31 29 29 27 27 24 24 22 22>,
- <1 38 38 37 37 35 35 33 33 30 30 28 28>,
- <1 34 34 34 34 34 34 33 33 30 30 28 28>,
- <2 33 33 33 33 33 33 33 33 30 30 28 28>;
-
- };
- r9 {
- channels = <40 40>;
- txs_delta = <0 0 0>;
- rates-ofdm = <36 36 36 36 36 36 34 34>;
- rates-mcs =
- <1 38 38 37 37 35 35 33 33 30 30>,
- <1 34 34 34 34 34 34 33 33 30 30>,
- <1 33 33 33 33 33 33 33 33 30 30>,
- <1 25 23 21 23 38 25 26 39 20 34>;
- rates-ru =
- <1 20 20 19 19 17 17 15 15 12 12 10 10>,
- <1 26 26 25 25 23 23 21 21 18 18 16 16>,
- <1 32 32 31 31 29 29 27 27 24 24 22 22>,
- <1 38 38 37 37 35 35 33 33 30 30 28 28>,
- <1 34 34 34 34 34 34 33 33 30 30 28 28>,
- <2 33 33 33 33 33 33 33 33 30 30 28 28>;
-
- };
- r10 {
- channels = <44 44>;
- txs_delta = <0 0 0>;
- rates-ofdm = <36 36 36 36 36 36 34 34>;
- rates-mcs =
- <1 38 38 37 37 35 35 33 33 30 30>,
- <1 34 34 34 34 34 34 33 33 30 30>,
- <1 33 33 33 33 33 33 33 33 30 30>,
- <1 31 24 22 33 38 36 24 30 27 27>;
- rates-ru =
- <1 20 20 19 19 17 17 15 15 12 12 10 10>,
- <1 26 26 25 25 23 23 21 21 18 18 16 16>,
- <1 32 32 31 31 29 29 27 27 24 24 22 22>,
- <1 38 38 37 37 35 35 33 33 30 30 28 28>,
- <1 34 34 34 34 34 34 33 33 30 30 28 28>,
- <2 33 33 33 33 33 33 33 33 30 30 28 28>;
-
- };
- r11 {
- channels = <48 48>;
- txs_delta = <0 0 0>;
- rates-ofdm = <36 36 36 36 36 36 34 34>;
- rates-mcs =
- <1 38 38 37 37 35 35 33 33 30 30>,
- <1 34 34 34 34 34 34 33 33 30 30>,
- <1 33 33 33 33 33 33 33 33 30 30>,
- <1 32 24 25 39 21 30 32 39 36 26>;
- rates-ru =
- <1 20 20 19 19 17 17 15 15 12 12 10 10>,
- <1 26 26 25 25 23 23 21 21 18 18 16 16>,
- <1 32 32 31 31 29 29 27 27 24 24 22 22>,
- <1 38 38 37 37 35 35 33 33 30 30 28 28>,
- <1 34 34 34 34 34 34 33 33 30 30 28 28>,
- <2 33 33 33 33 33 33 33 33 30 30 28 28>;
-
- };
- r12 {
- channels = <52 52>;
- txs_delta = <0 0 0>;
- rates-ofdm = <39 39 38 38 36 36 34 34>;
- rates-mcs =
- <1 42 42 38 38 35 35 33 33 30 30>,
- <1 37 37 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 39 29 39 31 25 32 30 21 35 37>;
- rates-ru =
- <1 24 24 20 20 17 17 15 15 12 12 10 10>,
- <1 30 30 26 26 23 23 21 21 18 18 16 16>,
- <1 36 36 32 32 29 29 27 27 24 24 22 22>,
- <1 42 42 38 38 35 35 33 33 30 30 28 28>,
- <1 37 37 37 37 35 35 33 33 30 30 28 28>,
- <2 36 36 36 36 35 35 33 33 30 30 28 28>;
-
- };
- r13 {
- channels = <56 56>;
- txs_delta = <0 0 0>;
- rates-ofdm = <39 39 38 38 36 36 34 34>;
- rates-mcs =
- <1 42 42 38 38 35 35 33 33 30 30>,
- <1 37 37 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 37 31 37 36 33 38 32 36 24 33>;
- rates-ru =
- <1 24 24 20 20 17 17 15 15 12 12 10 10>,
- <1 30 30 26 26 23 23 21 21 18 18 16 16>,
- <1 36 36 32 32 29 29 27 27 24 24 22 22>,
- <1 42 42 38 38 35 35 33 33 30 30 28 28>,
- <1 37 37 37 37 35 35 33 33 30 30 28 28>,
- <2 36 36 36 36 35 35 33 33 30 30 28 28>;
-
- };
- r14 {
- channels = <60 60>;
- txs_delta = <0 0 0>;
- rates-ofdm = <39 39 38 38 36 36 34 34>;
- rates-mcs =
- <1 42 42 38 38 35 35 33 33 30 30>,
- <1 37 37 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 22 38 22 22 31 38 24 31 38 39>;
- rates-ru =
- <1 24 24 20 20 17 17 15 15 12 12 10 10>,
- <1 30 30 26 26 23 23 21 21 18 18 16 16>,
- <1 36 36 32 32 29 29 27 27 24 24 22 22>,
- <1 42 42 38 38 35 35 33 33 30 30 28 28>,
- <1 37 37 37 37 35 35 33 33 30 30 28 28>,
- <2 36 36 36 36 35 35 33 33 30 30 28 28>;
-
- };
- r15 {
- channels = <64 64>;
- txs_delta = <0 0 0>;
- rates-ofdm = <39 39 38 38 36 36 34 34>;
- rates-mcs =
- <1 42 42 38 38 35 35 33 33 30 30>,
- <1 37 37 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 23 23 37 36 29 38 33 36 24 25>;
- rates-ru =
- <1 24 24 20 20 17 17 15 15 12 12 10 10>,
- <1 30 30 26 26 23 23 21 21 18 18 16 16>,
- <1 36 36 32 32 29 29 27 27 24 24 22 22>,
- <1 42 42 38 38 35 35 33 33 30 30 28 28>,
- <1 37 37 37 37 35 35 33 33 30 30 28 28>,
- <2 36 36 36 36 35 35 33 33 30 30 28 28>;
-
- };
- r16 {
- channels = <68 68>;
- txs_delta = <0 0 0>;
- rates-ofdm = <39 39 38 38 36 36 34 34>;
- rates-mcs =
- <1 42 42 38 38 35 35 33 33 30 30>,
- <1 37 37 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 21 36 31 29 38 22 37 29 38 32>;
- rates-ru =
- <1 24 24 20 20 17 17 15 15 12 12 10 10>,
- <1 30 30 26 26 23 23 21 21 18 18 16 16>,
- <1 36 36 32 32 29 29 27 27 24 24 22 22>,
- <1 42 42 38 38 35 35 33 33 30 30 28 28>,
- <1 37 37 37 37 35 35 33 33 30 30 28 28>,
- <2 36 36 36 36 35 35 33 33 30 30 28 28>;
-
- };
- r17 {
- channels = <72 72>;
- txs_delta = <0 0 0>;
- rates-ofdm = <39 39 38 38 36 36 34 34>;
- rates-mcs =
- <1 42 42 38 38 35 35 33 33 30 30>,
- <1 37 37 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 33 33 38 22 32 32 31 20 32 28>;
- rates-ru =
- <1 24 24 20 20 17 17 15 15 12 12 10 10>,
- <1 30 30 26 26 23 23 21 21 18 18 16 16>,
- <1 36 36 32 32 29 29 27 27 24 24 22 22>,
- <1 42 42 38 38 35 35 33 33 30 30 28 28>,
- <1 37 37 37 37 35 35 33 33 30 30 28 28>,
- <2 36 36 36 36 35 35 33 33 30 30 28 28>;
-
- };
- r18 {
- channels = <76 76>;
- txs_delta = <0 0 0>;
- rates-ofdm = <39 39 38 38 36 36 34 34>;
- rates-mcs =
- <1 42 42 38 38 35 35 33 33 30 30>,
- <1 37 37 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 27 31 27 37 27 25 39 31 21 26>;
- rates-ru =
- <1 24 24 20 20 17 17 15 15 12 12 10 10>,
- <1 30 30 26 26 23 23 21 21 18 18 16 16>,
- <1 36 36 32 32 29 29 27 27 24 24 22 22>,
- <1 42 42 38 38 35 35 33 33 30 30 28 28>,
- <1 37 37 37 37 35 35 33 33 30 30 28 28>,
- <2 36 36 36 36 35 35 33 33 30 30 28 28>;
-
- };
- r19 {
- channels = <80 80>;
- txs_delta = <0 0 0>;
- rates-ofdm = <39 39 38 38 36 36 34 34>;
- rates-mcs =
- <1 42 42 38 38 35 35 33 33 30 30>,
- <1 37 37 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 21 26 31 25 20 39 31 34 34 22>;
- rates-ru =
- <1 24 24 20 20 17 17 15 15 12 12 10 10>,
- <1 30 30 26 26 23 23 21 21 18 18 16 16>,
- <1 36 36 32 32 29 29 27 27 24 24 22 22>,
- <1 42 42 38 38 35 35 33 33 30 30 28 28>,
- <1 37 37 37 37 35 35 33 33 30 30 28 28>,
- <2 36 36 36 36 35 35 33 33 30 30 28 28>;
-
- };
- r20 {
- channels = <84 84>;
- txs_delta = <0 0 0>;
- rates-ofdm = <39 39 38 38 36 36 34 34>;
- rates-mcs =
- <1 42 42 38 38 35 35 33 33 30 30>,
- <1 37 37 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 26 27 26 21 25 27 22 25 35 26>;
- rates-ru =
- <1 24 24 20 20 17 17 15 15 12 12 10 10>,
- <1 30 30 26 26 23 23 21 21 18 18 16 16>,
- <1 36 36 32 32 29 29 27 27 24 24 22 22>,
- <1 42 42 38 38 35 35 33 33 30 30 28 28>,
- <1 37 37 37 37 35 35 33 33 30 30 28 28>,
- <2 36 36 36 36 35 35 33 33 30 30 28 28>;
-
- };
- r21 {
- channels = <88 88>;
- txs_delta = <0 0 0>;
- rates-ofdm = <39 39 38 38 36 36 34 34>;
- rates-mcs =
- <1 42 42 38 38 35 35 33 33 30 30>,
- <1 37 37 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 20 37 35 30 28 29 36 38 32 25>;
- rates-ru =
- <1 24 24 20 20 17 17 15 15 12 12 10 10>,
- <1 30 30 26 26 23 23 21 21 18 18 16 16>,
- <1 36 36 32 32 29 29 27 27 24 24 22 22>,
- <1 42 42 38 38 35 35 33 33 30 30 28 28>,
- <1 37 37 37 37 35 35 33 33 30 30 28 28>,
- <2 36 36 36 36 35 35 33 33 30 30 28 28>;
-
- };
- r22 {
- channels = <92 92>;
- txs_delta = <0 0 0>;
- rates-ofdm = <39 39 38 38 36 36 34 34>;
- rates-mcs =
- <1 42 42 38 38 35 35 33 33 30 30>,
- <1 37 37 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 30 37 37 20 22 34 23 26 21 35>;
- rates-ru =
- <1 24 24 20 20 17 17 15 15 12 12 10 10>,
- <1 30 30 26 26 23 23 21 21 18 18 16 16>,
- <1 36 36 32 32 29 29 27 27 24 24 22 22>,
- <1 42 42 38 38 35 35 33 33 30 30 28 28>,
- <1 37 37 37 37 35 35 33 33 30 30 28 28>,
- <2 36 36 36 36 35 35 33 33 30 30 28 28>;
-
- };
- r23 {
- channels = <96 96>;
- txs_delta = <0 0 0>;
- rates-ofdm = <39 39 38 38 36 36 34 34>;
- rates-mcs =
- <1 42 42 38 38 35 35 33 33 30 30>,
- <1 37 37 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 24 28 27 23 32 23 20 26 20 32>;
- rates-ru =
- <1 24 24 20 20 17 17 15 15 12 12 10 10>,
- <1 30 30 26 26 23 23 21 21 18 18 16 16>,
- <1 36 36 32 32 29 29 27 27 24 24 22 22>,
- <1 42 42 38 38 35 35 33 33 30 30 28 28>,
- <1 37 37 37 37 35 35 33 33 30 30 28 28>,
- <2 36 36 36 36 35 35 33 33 30 30 28 28>;
-
- };
- r24 {
- channels = <100 100>;
- txs_delta = <0 0 0>;
- rates-ofdm = <41 41 38 38 36 36 34 34>;
- rates-mcs =
- <1 40 40 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 30 27 25 39 31 35 28 37 27 28>;
- rates-ru =
- <1 22 22 19 19 17 17 15 15 12 12 10 10>,
- <1 28 28 25 25 23 23 21 21 18 18 16 16>,
- <1 34 34 31 31 29 29 27 27 24 24 22 22>,
- <1 40 40 37 37 35 35 33 33 30 30 28 28>,
- <1 36 36 36 36 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r25 {
- channels = <104 104>;
- txs_delta = <0 0 0>;
- rates-ofdm = <41 41 38 38 36 36 34 34>;
- rates-mcs =
- <1 40 40 37 37 35 35 33 33 30 30>,
- <1 36 36 36 36 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 24 22 26 38 28 24 34 38 32 37>;
- rates-ru =
- <1 22 22 19 19 17 17 15 15 12 12 10 10>,
- <1 28 28 25 25 23 23 21 21 18 18 16 16>,
- <1 34 34 31 31 29 29 27 27 24 24 22 22>,
- <1 40 40 37 37 35 35 33 33 30 30 28 28>,
- <1 36 36 36 36 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r26 {
- channels = <108 108>;
- txs_delta = <0 0 0>;
- rates-ofdm = <41 41 38 38 36 36 34 34>;
- rates-mcs =
- <1 40 40 37 37 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 25 26 21 34 38 38 31 23 36 38>;
- rates-ru =
- <1 22 22 19 19 17 17 15 15 12 12 10 10>,
- <1 28 28 25 25 23 23 21 21 18 18 16 16>,
- <1 34 34 31 31 29 29 27 27 24 24 22 22>,
- <1 40 40 37 37 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r27 {
- channels = <112 112>;
- txs_delta = <0 0 0>;
- rates-ofdm = <41 41 38 38 36 36 34 34>;
- rates-mcs =
- <1 40 40 37 37 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 38 38 28 26 21 39 35 26 35 21>;
- rates-ru =
- <1 22 22 19 19 17 17 15 15 12 12 10 10>,
- <1 28 28 25 25 23 23 21 21 18 18 16 16>,
- <1 34 34 31 31 29 29 27 27 24 24 22 22>,
- <1 40 40 37 37 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r28 {
- channels = <116 116>;
- txs_delta = <0 0 0>;
- rates-ofdm = <41 41 38 38 36 36 34 34>;
- rates-mcs =
- <1 40 40 37 37 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 21 20 22 39 36 21 31 39 36 39>;
- rates-ru =
- <1 22 22 19 19 17 17 15 15 12 12 10 10>,
- <1 28 28 25 25 23 23 21 21 18 18 16 16>,
- <1 34 34 31 31 29 29 27 27 24 24 22 22>,
- <1 40 40 37 37 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r29 {
- channels = <120 120>;
- txs_delta = <0 0 0>;
- rates-ofdm = <41 41 38 38 36 36 34 34>;
- rates-mcs =
- <1 40 40 37 37 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 39 21 34 39 28 25 28 26 26 36>;
- rates-ru =
- <1 22 22 19 19 17 17 15 15 12 12 10 10>,
- <1 28 28 25 25 23 23 21 21 18 18 16 16>,
- <1 34 34 31 31 29 29 27 27 24 24 22 22>,
- <1 40 40 37 37 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r30 {
- channels = <124 124>;
- txs_delta = <0 0 0>;
- rates-ofdm = <41 41 38 38 36 36 34 34>;
- rates-mcs =
- <1 40 40 37 37 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 22 34 36 32 32 21 29 28 29 21>;
- rates-ru =
- <1 22 22 19 19 17 17 15 15 12 12 10 10>,
- <1 28 28 25 25 23 23 21 21 18 18 16 16>,
- <1 34 34 31 31 29 29 27 27 24 24 22 22>,
- <1 40 40 37 37 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r31 {
- channels = <128 128>;
- txs_delta = <0 0 0>;
- rates-ofdm = <41 41 38 38 36 36 34 34>;
- rates-mcs =
- <1 40 40 37 37 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 29 20 37 33 26 39 32 35 27 27>;
- rates-ru =
- <1 22 22 19 19 17 17 15 15 12 12 10 10>,
- <1 28 28 25 25 23 23 21 21 18 18 16 16>,
- <1 34 34 31 31 29 29 27 27 24 24 22 22>,
- <1 40 40 37 37 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r32 {
- channels = <132 132>;
- txs_delta = <0 0 0>;
- rates-ofdm = <41 41 38 38 36 36 34 34>;
- rates-mcs =
- <1 40 40 37 37 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 30 27 24 30 27 24 35 31 38 39>;
- rates-ru =
- <1 22 22 19 19 17 17 15 15 12 12 10 10>,
- <1 28 28 25 25 23 23 21 21 18 18 16 16>,
- <1 34 34 31 31 29 29 27 27 24 24 22 22>,
- <1 40 40 37 37 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r33 {
- channels = <136 136>;
- txs_delta = <0 0 0>;
- rates-ofdm = <41 41 38 38 36 36 34 34>;
- rates-mcs =
- <1 40 40 37 37 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 36 37 38 34 22 33 32 23 24 37>;
- rates-ru =
- <1 22 22 19 19 17 17 15 15 12 12 10 10>,
- <1 28 28 25 25 23 23 21 21 18 18 16 16>,
- <1 34 34 31 31 29 29 27 27 24 24 22 22>,
- <1 40 40 37 37 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r34 {
- channels = <140 140>;
- txs_delta = <0 0 0>;
- rates-ofdm = <37 37 38 38 36 36 34 34>;
- rates-mcs =
- <1 38 38 36 36 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 32 29 37 27 27 25 21 31 35 20>;
- rates-ru =
- <1 20 20 18 18 17 17 15 15 12 12 10 10>,
- <1 26 26 24 24 23 23 21 21 18 18 16 16>,
- <1 32 32 30 30 29 29 27 27 24 24 22 22>,
- <1 38 38 36 36 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r35 {
- channels = <144 144>;
- txs_delta = <0 0 0>;
- rates-ofdm = <37 37 38 38 36 36 34 34>;
- rates-mcs =
- <1 38 38 36 36 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 38 39 29 38 29 22 33 35 38 28>;
- rates-ru =
- <1 20 20 18 18 17 17 15 15 12 12 10 10>,
- <1 26 26 24 24 23 23 21 21 18 18 16 16>,
- <1 32 32 30 30 29 29 27 27 24 24 22 22>,
- <1 38 38 36 36 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r36 {
- channels = <149 149>;
- txs_delta = <0 0 0>;
- rates-ofdm = <37 37 38 38 36 36 34 34>;
- rates-mcs =
- <1 38 38 36 36 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 25 25 30 32 37 31 24 29 38 21>;
- rates-ru =
- <1 20 20 18 18 17 17 15 15 12 12 10 10>,
- <1 26 26 24 24 23 23 21 21 18 18 16 16>,
- <1 32 32 30 30 29 29 27 27 24 24 22 22>,
- <1 38 38 36 36 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r37 {
- channels = <153 153>;
- txs_delta = <0 0 0>;
- rates-ofdm = <37 37 38 38 36 36 34 34>;
- rates-mcs =
- <1 38 38 36 36 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 27 25 34 27 36 30 26 36 21 34>;
- rates-ru =
- <1 20 20 18 18 17 17 15 15 12 12 10 10>,
- <1 26 26 24 24 23 23 21 21 18 18 16 16>,
- <1 32 32 30 30 29 29 27 27 24 24 22 22>,
- <1 38 38 36 36 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r38 {
- channels = <157 157>;
- txs_delta = <0 0 0>;
- rates-ofdm = <37 37 38 38 36 36 34 34>;
- rates-mcs =
- <1 38 38 36 36 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 30 32 21 22 25 28 34 39 23 36>;
- rates-ru =
- <1 20 20 18 18 17 17 15 15 12 12 10 10>,
- <1 26 26 24 24 23 23 21 21 18 18 16 16>,
- <1 32 32 30 30 29 29 27 27 24 24 22 22>,
- <1 38 38 36 36 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r39 {
- channels = <161 161>;
- txs_delta = <0 0 0>;
- rates-ofdm = <37 37 38 38 36 36 34 34>;
- rates-mcs =
- <1 38 38 36 36 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 26 23 35 27 38 27 21 34 39 27>;
- rates-ru =
- <1 20 20 18 18 17 17 15 15 12 12 10 10>,
- <1 26 26 24 24 23 23 21 21 18 18 16 16>,
- <1 32 32 30 30 29 29 27 27 24 24 22 22>,
- <1 38 38 36 36 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r40 {
- channels = <165 165>;
- txs_delta = <0 0 0>;
- rates-ofdm = <37 37 38 38 36 36 34 34>;
- rates-mcs =
- <1 38 38 36 36 35 35 33 33 30 30>,
- <1 40 40 38 38 35 35 33 33 30 30>,
- <1 35 35 35 35 35 35 33 33 30 30>,
- <1 21 24 20 31 28 31 20 21 29 27>;
- rates-ru =
- <1 20 20 18 18 17 17 15 15 12 12 10 10>,
- <1 26 26 24 24 23 23 21 21 18 18 16 16>,
- <1 32 32 30 30 29 29 27 27 24 24 22 22>,
- <1 38 38 36 36 35 35 33 33 30 30 28 28>,
- <1 40 40 38 38 35 35 33 33 30 30 28 28>,
- <2 35 35 35 35 35 35 33 33 30 30 28 28>;
-
- };
- r41 {
- channels = <169 169>;
- txs_delta = <0 0 0>;
- rates-ofdm = <36 31 21 37 27 38 38 37>;
- rates-mcs =
- <1 35 37 34 32 25 25 24 27 21 29>,
- <1 34 33 36 26 38 38 37 34 25 29>,
- <1 33 35 21 22 39 24 32 33 37 38>,
- <1 34 28 30 26 22 37 29 29 31 26>;
- rates-ru =
- <1 25 25 37 23 29 39 37 26 27 20 39 29>,
- <1 39 37 39 32 36 27 32 38 33 27 33 24>,
- <1 21 27 35 35 37 39 26 33 29 21 27 36>,
- <1 29 27 26 24 38 32 21 38 27 30 32 25>,
- <1 21 22 36 33 28 32 31 24 35 22 22 20>,
- <1 39 34 24 21 36 30 33 33 29 35 36 26>,
- <1 28 38 34 27 26 33 35 28 28 25 29 24>;
-
- };
- r42 {
- channels = <173 173>;
- txs_delta = <0 0 0>;
- rates-ofdm = <23 32 34 39 26 33 22 30>;
- rates-mcs =
- <1 22 25 22 25 28 21 20 24 30 39>,
- <1 26 30 32 35 32 37 21 38 36 30>,
- <1 35 33 27 24 37 24 28 29 21 32>,
- <1 31 24 29 23 38 30 34 31 38 20>;
- rates-ru =
- <1 38 24 39 20 36 25 39 26 33 35 25 38>,
- <1 29 26 31 33 39 37 36 39 20 26 36 21>,
- <1 24 27 22 30 33 31 33 23 32 29 35 28>,
- <1 34 33 25 25 35 37 22 31 20 20 27 35>,
- <1 22 28 35 27 20 26 25 39 20 25 37 21>,
- <1 35 35 28 23 27 20 29 25 31 33 20 38>,
- <1 25 29 31 24 30 35 36 32 34 31 37 30>;
-
- };
- r43 {
- channels = <177 177>;
- txs_delta = <0 0 0>;
- rates-ofdm = <26 20 32 34 37 35 39 31>;
- rates-mcs =
- <1 28 20 39 30 31 22 30 39 21 22>,
- <1 34 38 35 25 38 33 34 23 38 34>,
- <1 34 32 34 25 29 24 32 29 22 36>,
- <1 20 26 36 37 38 24 29 39 39 27>;
- rates-ru =
- <1 28 35 34 20 22 22 27 22 28 33 23 38>,
- <1 22 21 27 26 36 31 39 32 25 21 37 23>,
- <1 25 30 37 28 39 32 30 26 24 25 22 34>,
- <1 30 20 33 35 20 34 24 22 38 31 24 21>,
- <1 31 22 24 26 27 23 33 24 27 35 32 28>,
- <1 25 34 33 27 34 31 33 20 38 31 24 23>,
- <1 27 30 28 36 33 33 21 36 36 33 34 20>;
-
- };
- r44 {
- channels = <181 181>;
- txs_delta = <0 0 0>;
- rates-ofdm = <36 30 37 33 32 30 20 38>;
- rates-mcs =
- <1 20 26 22 38 26 36 28 24 29 31>,
- <1 20 26 29 35 38 31 33 21 37 29>,
- <1 39 30 24 35 22 31 30 37 23 37>,
- <1 38 21 30 37 24 34 29 29 23 26>;
- rates-ru =
- <1 36 24 21 23 39 28 21 36 38 30 24 33>,
- <1 38 24 29 37 30 23 29 35 23 33 39 30>,
- <1 31 33 26 38 32 29 21 30 22 28 30 20>,
- <1 30 32 27 33 38 24 30 31 25 22 20 21>,
- <1 34 38 37 24 33 35 33 31 22 28 21 31>,
- <1 38 29 34 28 26 23 37 39 34 37 22 36>,
- <1 36 23 21 24 25 25 20 35 33 24 24 22>;
- };
- };
-
- };
- };
- };
-
- pcie_intc0: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
- };
-
- pcie1: pcie@1,0 {
- device_type = "pci";
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc1 1>,
- <0 0 0 2 &pcie_intc1 2>,
- <0 0 0 3 &pcie_intc1 3>,
- <0 0 0 4 &pcie_intc1 4>;
- pcie-port = <1>;
- num-lanes = <1>;
- status = "okay";
- pcie_intc1: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
- };
- };
-
- wdma{
- compatible = "en751221,wdma";
- reg = <0x1fa06000 0x400 >,
- <0x1fa06400 0x400 >;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wed{
- compatible = "en751221,wed";
- wed_num = <2>;
- pci_slot_map = <0>, <1>;
- reg = <0x1fa02000 0xb00 >,
- <0x1fa03000 0xb00 >;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wed2{
- compatible = "en751221,wed2";
- wed_num = <2>;
- pci_slot_map = <0>, <1>;
- reg = <0x1fa02000 0xb00 >,
- <0x1fa03000 0xb00 >;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wed_test{
- compatible = "en751221,wed_test";
- wed_num = <2>;
- reg = <0x1fa02b00 0x100 >,
- <0x1fa03b00 0x100 >;
- };
-
-
-
- i2c@1fbf8000 {
- compatible = "econet,ecnt-i2c";
- reg = <0x1fbf8000 0x65>;
- };
-
- gdump@1fbf9000 {
- compatible = "econet,ecnt-gdump";
- reg = <0x1fbf9000 0x84>;
- };
-
- crypto_k@1fb70000 {
- compatible = "econet,ecnt-crypto_k";
- reg = <0x1fb70000 0x804>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- trng@1faa1000 {
- compatible = "econet,ecnt-trng";
- reg = <0x1faa1000 0xc04>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gdma@1fb30000 {
- compatible = "econet,ecnt-gdma";
- reg = <0x1fb30000 0x2b0>;
- };
-
- xsi@1fa60000 {
- compatible = "econet,ecnt-xsi";
- reg = <0x1fa60000 0x300>, //hsgmii ae
- <0x1fa70000 0x300>, //hsgmii pcie0
- <0x1fa71000 0x300>, //hsgmii pcie1
- <0x1fa80000 0x300>; //hsgmii usb
- };
-
- i2c_slave@1fbe3300 {
- compatible = "econet,ecnt-i2c_slave";
- reg = <0x1fbe3300 0x10>;
- dev0_addr = <0x60>;
- dev1_addr = <0x62>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- uart1: serial@1fbf0000 {
- compatible = "econet,ecnt-uart1";
- reg = <0x1fbf0000 0x30>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- //status = "disabled";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
};
- uart2: serial@1fbf0300 {
- compatible = "econet,ecnt-uart2";
- reg = <0x1fbf0300 0x30>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- //status = "disabled";
- };
-/* Generic led driver is not compatible yet
- leds {
- compatible = "gpio-leds";
- led1 {
- label = "green:led1";
- gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
- };
- led2 {
- label = "red:led2";
- gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
- };
- led3 {
- label = "blue:led3";
- gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio0: gpio@1fbf0200 {
- compatible = "airoha,en7523-gpio";
- reg = <0x1fbf0204 0x4>,
- <0x1fbf0200 0x4>,
- <0x1fbf0220 0x4>,
- <0x1fbf0214 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio1: gpio@1fbf0270 {
- compatible = "airoha,en7523-gpio";
- reg = <0x1fbf0270 0x4>,
- <0x1fbf0260 0x4>,
- <0x1fbf0264 0x4>,
- <0x1fbf0278 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-*/
- gpio@1fbf0200 {
- compatible = "econet,ecnt-gpio";
- reg = <0x1fbf0200 0x80>;
- };
-
- spi_ctrl: spi_controller@1fa10000 {
- compatible = "econet,ecnt-spi_ctrl";
- reg = <0x1fa10000 0x140>, //SPI Controller Base
- <0x00000000 0x1000>; //SPI Controller auto read interrupt test
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- spi_spi2nfi: spi_spi2nfi@1fa11000 {
- compatible = "econet,ecnt-spi2nfi";
- reg = <0x1fa11000 0x160>; //NFI2SPI
- };
-
- spi_ecc: spi_ecc@1fa12000 {
- compatible = "econet,ecnt-spi_ecc";
- reg = <0x1fa12000 0x150>; //NFI ECC
- };
-
- frame_engine: frame_engine@1fb50000 {
- compatible = "econet,ecnt-frame_engine";
- reg = <0x1fb50000 0x2600>, //FE + PPE
- <0x1fb54000 0x4000>, //QDMA
- <0x1fb58000 0x8000>; //SWITCH
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT1 21+16
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT2 39+16
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT3 40+16
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT4 41+16
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT1 22+16
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT2 42+16
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT3 43+16
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT4 44+16
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, // FE ERROR INTR 33+16
- <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; // PDMA INTR 48+16
- };
-
- spi_nor_flash: snor {
- compatible = "econet,ecnt-snor";
- spi-controller = <&spi_ctrl>;
- };
-
- nand_flash: nand@1fa10000 {
- compatible = "econet,ecnt-nand";
- spi-controller = <&spi_ctrl>;
- spi2nfi = <&spi_spi2nfi>;
- spi-ecc = <&spi_ecc>;
- };
-
- hsdma: dma-controller@1fa01800 {
- compatible = "econet,en7523-hsdma";
- reg = <0x1fa01800 0x300>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- dma-channels = <2>;
- dma-requests = <2>;
- };
-
- cpu_top@1efb0000 {
- compatible = "econet,ecnt-cpu_top";
- reg = <0x1efbc800 0x10>; //CTRL
- };
-
- xpon_mac: xpon@1fb64000 {
- compatible = "econet,ecnt-xpon";
- reg = <0x1fb64000 0x3e8>,
- <0x1fb66000 0x23c>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, // XPON MAC INT 26+16
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;// DYINGGASP INT 18+16
- };
-
- xhci_hcd: xhci@1fab0000 {
- compatible = "econet,ecnt-xhci";
- reg = <0x1fab0000 0x3e00>, //MAC base address
- <0x1fab3e00 0x100>; //IPPC base address
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pon_phy: pon_phy@1faf0000 {
- compatible = "econet,ecnt-pon_phy";
- reg = <0x1faf0000 0x800>, // PON_PHY_ASIC_RG range
- <0x1fa2ff24 0x4>, // PON_PHY_FPGA_RG_TX_OFF
- <0x1faf3000 0xfff>, // PON_PHY_ASIC_RG range2
- <0x1faf4000 0xfff>; // PON_PHY_ASIC_RG range3
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; // XPON_PHY_INTR 27+16
- };
-
- pcm@bfbd0000 {
- compatible = "econet,ecnt-pcm";
- reg = <0x1fbd0000 0x4fff>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- i2s@1fbe2200 {
- compatible = "econet,ecnt-i2s";
- reg = <0x1fbe2200 0xfc>,
- <0x1fbe2e00 0x114>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pcie_phy: pcie_phy@1fa93700 {
- compatible = "econet,en7523-pcie_phy";
- reg = <0x1fa93700 0x568>, //PC0 RG range
- <0x1fa95700 0x568>; //PC1 RG range
- };
- pon_hsgmii: pon_hsgmii@1fa65000 {
- compatible = "econet,ecnt-pon_hsgmii";
- reg = <0x1fa65100 0x4a0>, //PCS mode1 range
- <0x1fa65a00 0x1ac>, //PCS mode2 range
- <0x1fa65e00 0x64>, //AN range
- <0x1fa66000 0xdc>; //rate adaption range
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; // pon_hsgmii INT 50+16
- };
- sgmii_p0: sgmii_p0@1fa72000 {
- compatible = "econet,ecnt-sgmii";
- reg = <0x1fa72100 0x4a0>, //PCS mode1 range
- <0x1fa72a00 0x160>, //PCS mode2 range
- <0x1fa72000 0x64>, //AN range
- <0x1fa72600 0xdc>, //rate adaption range
- <0x1fa72c00 0x3b0>; //phya
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; // pc0_hsgmii INT 135+16
- int_name = "sgmii_pcie0";
- int_id = <0>;
- };
- sgmii_p1: sgmii_p1@1fa77000 {
- compatible = "econet,ecnt-sgmii";
- reg = <0x1fa77100 0x4a0>, //PCS mode1 range
- <0x1fa77a00 0x160>, //PCS mode2 range
- <0x1fa77000 0x64>, //AN range
- <0x1fa77600 0xdc>, //rate adaption range
- <0x1fa77c00 0x3b0>; //phya
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; // pc1_hsgmii INT 136+16
- int_name = "sgmii_pcie1";
- int_id = <1>;
- };
- sgmii_u0: sgmii_u0@1fa81000 {
- compatible = "econet,ecnt-sgmii";
- reg = <0x1fa81100 0x4a0>, //PCS mode1 range
- <0x1fa81a00 0x160>, //PCS mode2 range
- <0x1fa81000 0x64>, //AN range
- <0x1fa81600 0xdc>, //rate adaption range
- <0x1fa81c00 0x3b0>; //phya
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; // usb_hsgmii INT 137+16
- int_name = "sgmii_usb0";
- int_id = <2>;
- };
-
- usb_phy@1fad0000 {
- compatible = "econet,ecnt-usb_phy";
- reg = <0x1fad0000 0x1fff>;
- };
-
- thermal_phy: thermal_phy@1efbd000 {
- compatible = "econet,ecnt-thermal_phy";
- reg = <0x1efbd000 0x0fff>; //ptp_thermal_ctrl
- };
-
-
};
diff --git a/iopsys-econet/dts/en7523_evb.dts b/iopsys-econet/dts/en7523_evb.dts
index f15036cdc..f673ae6be 100755
--- a/iopsys-econet/dts/en7523_evb.dts
+++ b/iopsys-econet/dts/en7523_evb.dts
@@ -1,491 +1,14 @@
-
-
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/gpio.h>
/dts-v1/;
-/ {
- compatible = "econet,en7523";
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <1>;
+#include "en75xx-base.dtsi"
- chosen {
+/ {
+ chosen {
bootargs = "root=/dev/mtdblock3 ro console=ttyS0,115200n8 earlycon init=/sbin/init";
stdout-path = &uart1;
};
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- atf-reserved-memory@80000000 {
- compatible = "econet,en7523-atf-reserved-memory";
- no-map;
- reg = <0x80000000 0x40000>;
- };
-
- npu_reserved: npu_binary@84000000 {
- no-map;
- reg = <0x84000000 0x100000>;
- };
-
- /* pstore memory reservations */
- #include "en7523_pstore.dtsi"
-
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
- core1 {
- cpu = <&cpu1>;
- };
- };
- };
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0>;
- enable-method = "psci";
- clock-frequency = <80000000>;
- next-level-cache = <&L2_0>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x1>;
- enable-method = "psci";
- clock-frequency = <80000000>;
- next-level-cache = <&L2_0>;
- };
-
- L2_0: l2-cache0 {
- compatible = "cache";
- };
- };
-
- gic: interrupt-controller@09000000 {
- compatible = "arm,gic-v3";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x09000000 0x20000>,
- <0x09080000 0x80000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
-
- its: gic-its@09020000 {
- compatible = "arm,gic-v3-its";
- msi-controller;
- #msi-cell = <1>;
- reg = <0x090200000 0x20000>;
- };
- };
-
-
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- clock-frequency = <25000000>;
- };
-
- pmu {
- //compatible = "arm,armv8-pmuv3";
- compatible = "arm,cortex-a15-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- npu@1e800000 {
- compatible = "econet,ecnt-npu";
- reg = <0x1e800000 0x60000>, //NPU 384K SRAM
- <0x1e900000 0x313000>; //NPU 16K SRAM, Registers
- memory-region = <&npu_reserved>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 102+16 tr done
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 105+16 hadap irq0
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; //mbox2host irq
- };
-
- apb_timer1: apb_timer1@1fbf0100 {
- compatible = "econet,ecnt-timer";
- reg = <0x1fbf0100 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x40000000>;
- };
-
- rbus@1fa00000 {
- compatible = "econet,ecnt-rbus";
- reg = <0x1fa00000 0x1000>; //RBus Core
- };
-
- sram@1fa40000 {
- compatible = "econet,ecnt-sram";
- reg = <0x1fa40000 0x8000>, //GDMP SRAM
- <0x08000000 0x40000>, //L2C SRAM (only for CPU internal access)
- <0x1EFC0000 0x40000>, //L2C SRAM (only for CPU/NPU/GDMA/SPI/Crypto/WOE external access via pbus)
- <0x1E880000 0x40000>, //L2C SRAM (only for CPU/NPU/HSDMA/PCIE external access via npu_rbus)
- <0x1fbe3000 0x200>; //I2C_SLAVE SRAM
- };
-
- scu@1fb00000 {
- compatible = "econet,ecnt-scu";
- reg = <0x1fb00000 0x960>, //NP SCU
- <0x1fa20000 0x360>, //CHIP SCU
- <0x1fa2FF30 0x10>; //Rbus clk ctl for FPGA
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pcie@0x1fa91000 {
- compatible = "ecnt,pcie-en7523";
- device_type = "pci";
- reg = <0x1fa91000 0x1000>,
- <0x1fa92000 0x1000>,
- <0x1fa90000 0x1000>, /* pcie top*/
- <0x1a100000 0x1000>, /* switch lane */
- <0x1a148000 0x1000>, /* 4, rc0 phy base, for change xtal setting */
- <0x1a14a000 0x1000>; /* 5, rc1 phy base, for change xtal setting */
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, //23+16
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; //24+16
- bus-range = <0x00 0xff>;
- #address-cells = <3>;
- #size-cells = <2>;
- /* change xtal for 40M, default is 25M */
- /* change-xtal; */
- /* disable io coherent for RC and EP default. */
- /*dma-coherent;*/
- ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
-
- pcie0: pcie@0,0 {
- device_type = "pci";
- reg = <0x0000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc0 1>,
- <0 0 0 2 &pcie_intc0 2>,
- <0 0 0 3 &pcie_intc0 3>,
- <0 0 0 4 &pcie_intc0 4>;
- pcie-port = <0>;
- num-lanes = <1>;
- status = "okay";
- pcie_intc0: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
- };
-
- pcie1: pcie@1,0 {
- device_type = "pci";
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc1 1>,
- <0 0 0 2 &pcie_intc1 2>,
- <0 0 0 3 &pcie_intc1 3>,
- <0 0 0 4 &pcie_intc1 4>;
- pcie-port = <1>;
- num-lanes = <1>;
- status = "okay";
- pcie_intc1: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
- };
- };
-
- wdma{
- compatible = "en751221,wdma";
- reg = <0x1fa06000 0x400 >,
- <0x1fa06400 0x400 >;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wed{
- compatible = "en751221,wed";
- wed_num = <2>;
- pci_slot_map = <0>, <1>;
- reg = <0x1fa02000 0xb00 >,
- <0x1fa03000 0xb00 >;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wed2{
- compatible = "en751221,wed2";
- wed_num = <2>;
- pci_slot_map = <0>, <1>;
- reg = <0x1fa02000 0xb00 >,
- <0x1fa03000 0xb00 >;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wed_test{
- compatible = "en751221,wed_test";
- wed_num = <2>;
- reg = <0x1fa02b00 0x100 >,
- <0x1fa03b00 0x100 >;
- };
-
-
-
- i2c@1fbf8000 {
- compatible = "econet,ecnt-i2c";
- reg = <0x1fbf8000 0x65>;
- };
-
- gdump@1fbf9000 {
- compatible = "econet,ecnt-gdump";
- reg = <0x1fbf9000 0x84>;
- };
-
- crypto_k@1fb70000 {
- compatible = "econet,ecnt-crypto_k";
- reg = <0x1fb70000 0x804>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- trng@1faa1000 {
- compatible = "econet,ecnt-trng";
- reg = <0x1faa1000 0xc04>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gdma@1fb30000 {
- compatible = "econet,ecnt-gdma";
- reg = <0x1fb30000 0x2b0>;
- };
-
- xsi@1fa60000 {
- compatible = "econet,ecnt-xsi";
- reg = <0x1fa60000 0x300>, //hsgmii ae
- <0x1fa70000 0x300>, //hsgmii pcie0
- <0x1fa71000 0x300>, //hsgmii pcie1
- <0x1fa80000 0x300>; //hsgmii usb
- };
-
- i2c_slave@1fbe3300 {
- compatible = "econet,ecnt-i2c_slave";
- reg = <0x1fbe3300 0x10>;
- dev0_addr = <0x60>;
- dev1_addr = <0x62>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- uart1: serial@1fbf0000 {
- compatible = "econet,ecnt-uart1";
- reg = <0x1fbf0000 0x30>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- //status = "disabled";
- };
- uart2: serial@1fbf0300 {
- compatible = "econet,ecnt-uart2";
- reg = <0x1fbf0300 0x30>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- //status = "disabled";
- };
- gpio@1fbf0200 {
- compatible = "econet,ecnt-gpio";
- reg = <0x1fbf0200 0x80>;
- };
-
- spi_ctrl: spi_controller@1fa10000 {
- compatible = "econet,ecnt-spi_ctrl";
- reg = <0x1fa10000 0x140>, //SPI Controller Base
- <0x00000000 0x1000>; //SPI Controller auto read interrupt test
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- spi_spi2nfi: spi_spi2nfi@1fa11000 {
- compatible = "econet,ecnt-spi2nfi";
- reg = <0x1fa11000 0x160>; //NFI2SPI
- };
-
- spi_ecc: spi_ecc@1fa12000 {
- compatible = "econet,ecnt-spi_ecc";
- reg = <0x1fa12000 0x150>; //NFI ECC
- };
-
- frame_engine: frame_engine@1fb50000 {
- compatible = "econet,ecnt-frame_engine";
- reg = <0x1fb50000 0x2600>, //FE + PPE
- <0x1fb54000 0x4000>, //QDMA
- <0x1fb58000 0x8000>; //SWITCH
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT1 21+16
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT2 39+16
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT3 40+16
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT4 41+16
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT1 22+16
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT2 42+16
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT3 43+16
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT4 44+16
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, // FE ERROR INTR 33+16
- <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; // PDMA INTR 48+16
- };
-
- spi_nor_flash: snor {
- compatible = "econet,ecnt-snor";
- spi-controller = <&spi_ctrl>;
- };
-
- nand_flash: nand@1fa10000 {
- compatible = "econet,ecnt-nand";
- spi-controller = <&spi_ctrl>;
- spi2nfi = <&spi_spi2nfi>;
- spi-ecc = <&spi_ecc>;
- };
-
- hsdma: dma-controller@1fa01800 {
- compatible = "econet,en7523-hsdma";
- reg = <0x1fa01800 0x300>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- dma-channels = <2>;
- dma-requests = <2>;
- };
-
- cpu_top@1efb0000 {
- compatible = "econet,ecnt-cpu_top";
- reg = <0x1efbc800 0x10>; //CTRL
- };
-
- xpon_mac: xpon@1fb64000 {
- compatible = "econet,ecnt-xpon";
- reg = <0x1fb64000 0x3e8>,
- <0x1fb66000 0x23c>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, // XPON MAC INT 26+16
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;// DYINGGASP INT 18+16
- };
-
- xhci_hcd: xhci@1fab0000 {
- compatible = "econet,ecnt-xhci";
- reg = <0x1fab0000 0x3e00>, //MAC base address
- <0x1fab3e00 0x100>; //IPPC base address
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pon_phy: pon_phy@1faf0000 {
- compatible = "econet,ecnt-pon_phy";
- reg = <0x1faf0000 0x800>, // PON_PHY_ASIC_RG range
- <0x1fa2ff24 0x4>, // PON_PHY_FPGA_RG_TX_OFF
- <0x1faf3000 0xfff>, // PON_PHY_ASIC_RG range2
- <0x1faf4000 0xfff>; // PON_PHY_ASIC_RG range3
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; // XPON_PHY_INTR 27+16
- };
-
- pcm@bfbd0000 {
- compatible = "econet,ecnt-pcm";
- reg = <0x1fbd0000 0x4fff>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- i2s@1fbe2200 {
- compatible = "econet,ecnt-i2s";
- reg = <0x1fbe2200 0xfc>,
- <0x1fbe2e00 0x114>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pcie_phy: pcie_phy@1fa93700 {
- compatible = "econet,en7523-pcie_phy";
- reg = <0x1fa93700 0x568>, //PC0 RG range
- <0x1fa95700 0x568>; //PC1 RG range
- };
- pon_hsgmii: pon_hsgmii@1fa65000 {
- compatible = "econet,ecnt-pon_hsgmii";
- reg = <0x1fa65100 0x4a0>, //PCS mode1 range
- <0x1fa65a00 0x1ac>, //PCS mode2 range
- <0x1fa65e00 0x64>, //AN range
- <0x1fa66000 0xdc>; //rate adaption range
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; // pon_hsgmii INT 50+16
- };
- sgmii_p0: sgmii_p0@1fa72000 {
- compatible = "econet,ecnt-sgmii";
- reg = <0x1fa72100 0x4a0>, //PCS mode1 range
- <0x1fa72a00 0x160>, //PCS mode2 range
- <0x1fa72000 0x64>, //AN range
- <0x1fa72600 0xdc>, //rate adaption range
- <0x1fa72c00 0x3b0>; //phya
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; // pc0_hsgmii INT 135+16
- int_name = "sgmii_pcie0";
- int_id = <0>;
- };
- sgmii_p1: sgmii_p1@1fa77000 {
- compatible = "econet,ecnt-sgmii";
- reg = <0x1fa77100 0x4a0>, //PCS mode1 range
- <0x1fa77a00 0x160>, //PCS mode2 range
- <0x1fa77000 0x64>, //AN range
- <0x1fa77600 0xdc>, //rate adaption range
- <0x1fa77c00 0x3b0>; //phya
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; // pc1_hsgmii INT 136+16
- int_name = "sgmii_pcie1";
- int_id = <1>;
- };
- sgmii_u0: sgmii_u0@1fa81000 {
- compatible = "econet,ecnt-sgmii";
- reg = <0x1fa81100 0x4a0>, //PCS mode1 range
- <0x1fa81a00 0x160>, //PCS mode2 range
- <0x1fa81000 0x64>, //AN range
- <0x1fa81600 0xdc>, //rate adaption range
- <0x1fa81c00 0x3b0>; //phya
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; // usb_hsgmii INT 137+16
- int_name = "sgmii_usb0";
- int_id = <2>;
- };
-
- usb_phy@1fad0000 {
- compatible = "econet,ecnt-usb_phy";
- reg = <0x1fad0000 0x1fff>;
- };
-
- thermal_phy: thermal_phy@1efbd000 {
- compatible = "econet,ecnt-thermal_phy";
- reg = <0x1efbd000 0x0fff>; //ptp_thermal_ctrl
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; // ptp_therm INT 7+16
- int_name = "ptp_therm";
- };
-
-
};
diff --git a/iopsys-econet/dts/en75xx-base.dtsi b/iopsys-econet/dts/en75xx-base.dtsi
new file mode 100755
index 000000000..cdd2d7c81
--- /dev/null
+++ b/iopsys-econet/dts/en75xx-base.dtsi
@@ -0,0 +1,517 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+
+/ {
+ compatible = "econet,en7523";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlycon init=/sbin/init";
+ stdout-path = &uart1;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ atf-reserved-memory@80000000 {
+ compatible = "econet,en7523-atf-reserved-memory";
+ no-map;
+ reg = <0x80000000 0x40000>;
+ };
+
+ npu_reserved: npu_binary@84000000 {
+ no-map;
+ reg = <0x84000000 0x100000>;
+ };
+
+ /* pstore memory reservations */
+ #include "en7523_pstore.dtsi"
+
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ clock-frequency = <80000000>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ clock-frequency = <80000000>;
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ gic: interrupt-controller@09000000 {
+ compatible = "arm,gic-v3";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x09000000 0x20000>,
+ <0x09080000 0x80000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+
+ its: gic-its@09020000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cell = <1>;
+ reg = <0x090200000 0x20000>;
+ };
+ };
+
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <25000000>;
+ };
+
+ pmu {
+ //compatible = "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a15-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ npu@1e800000 {
+ compatible = "econet,ecnt-npu";
+ reg = <0x1e800000 0x60000>, //NPU 384K SRAM
+ <0x1e900000 0x313000>; //NPU 16K SRAM, Registers
+ memory-region = <&npu_reserved>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 102+16 tr done
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 105+16 hadap irq0
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; //mbox2host irq
+ };
+
+ apb_timer1: apb_timer1@1fbf0100 {
+ compatible = "econet,ecnt-timer";
+ reg = <0x1fbf0100 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ rbus@1fa00000 {
+ compatible = "econet,ecnt-rbus";
+ reg = <0x1fa00000 0x1000>; //RBus Core
+ };
+
+ sram@1fa40000 {
+ compatible = "econet,ecnt-sram";
+ reg = <0x1fa40000 0x8000>, //GDMP SRAM
+ <0x08000000 0x40000>, //L2C SRAM (only for CPU internal access)
+ <0x1EFC0000 0x40000>, //L2C SRAM (only for CPU/NPU/GDMA/SPI/Crypto/WOE external access via pbus)
+ <0x1E880000 0x40000>, //L2C SRAM (only for CPU/NPU/HSDMA/PCIE external access via npu_rbus)
+ <0x1fbe3000 0x200>; //I2C_SLAVE SRAM
+ };
+
+ scu@1fb00000 {
+ compatible = "econet,ecnt-scu";
+ reg = <0x1fb00000 0x960>, //NP SCU
+ <0x1fa20000 0x360>, //CHIP SCU
+ <0x1fa2FF30 0x10>; //Rbus clk ctl for FPGA
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pcie@0x1fa91000 {
+ compatible = "ecnt,pcie-en7523";
+ device_type = "pci";
+ reg = <0x1fa91000 0x1000>,
+ <0x1fa92000 0x1000>,
+ <0x1fa90000 0x1000>, /* pcie top*/
+ <0x1a100000 0x1000>, /* switch lane */
+ <0x1a148000 0x1000>, /* 4, rc0 phy base, for change xtal setting */
+ <0x1a14a000 0x1000>; /* 5, rc1 phy base, for change xtal setting */
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, //23+16
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; //24+16
+ bus-range = <0x00 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ /* change xtal for 40M, default is 25M */
+ /* change-xtal; */
+ /* disable io coherent for RC and EP default. */
+ /*dma-coherent;*/
+ ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
+
+ pcie0: pcie@0,0 {
+ device_type = "pci";
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 1>,
+ <0 0 0 2 &pcie_intc0 2>,
+ <0 0 0 3 &pcie_intc0 3>,
+ <0 0 0 4 &pcie_intc0 4>;
+ pcie-port = <0>;
+ num-lanes = <1>;
+ status = "okay";
+
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@1,0 {
+ device_type = "pci";
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 1>,
+ <0 0 0 2 &pcie_intc1 2>,
+ <0 0 0 3 &pcie_intc1 3>,
+ <0 0 0 4 &pcie_intc1 4>;
+ pcie-port = <1>;
+ num-lanes = <1>;
+ status = "okay";
+
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ wdma{
+ compatible = "en751221,wdma";
+ reg = <0x1fa06000 0x400 >,
+ <0x1fa06400 0x400 >;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wed{
+ compatible = "en751221,wed";
+ wed_num = <2>;
+ pci_slot_map = <0>, <1>;
+ reg = <0x1fa02000 0xb00 >,
+ <0x1fa03000 0xb00 >;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wed2{
+ compatible = "en751221,wed2";
+ wed_num = <2>;
+ pci_slot_map = <0>, <1>;
+ reg = <0x1fa02000 0xb00 >,
+ <0x1fa03000 0xb00 >;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wed_test{
+ compatible = "en751221,wed_test";
+ wed_num = <2>;
+ reg = <0x1fa02b00 0x100 >,
+ <0x1fa03b00 0x100 >;
+ };
+
+ i2c@1fbf8000 {
+ compatible = "econet,ecnt-i2c";
+ reg = <0x1fbf8000 0x65>;
+ };
+
+ gdump@1fbf9000 {
+ compatible = "econet,ecnt-gdump";
+ reg = <0x1fbf9000 0x84>;
+ };
+
+ crypto_k@1fb70000 {
+ compatible = "econet,ecnt-crypto_k";
+ reg = <0x1fb70000 0x804>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ trng@1faa1000 {
+ compatible = "econet,ecnt-trng";
+ reg = <0x1faa1000 0xc04>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gdma@1fb30000 {
+ compatible = "econet,ecnt-gdma";
+ reg = <0x1fb30000 0x2b0>;
+ };
+
+ xsi@1fa60000 {
+ compatible = "econet,ecnt-xsi";
+ reg = <0x1fa60000 0x300>, //hsgmii ae
+ <0x1fa70000 0x300>, //hsgmii pcie0
+ <0x1fa71000 0x300>, //hsgmii pcie1
+ <0x1fa80000 0x300>; //hsgmii usb
+ };
+
+ i2c_slave@1fbe3300 {
+ compatible = "econet,ecnt-i2c_slave";
+ reg = <0x1fbe3300 0x10>;
+ dev0_addr = <0x60>;
+ dev1_addr = <0x62>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart1: serial@1fbf0000 {
+ compatible = "econet,ecnt-uart1";
+ reg = <0x1fbf0000 0x30>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ //status = "disabled";
+ };
+
+ uart2: serial@1fbf0300 {
+ compatible = "econet,ecnt-uart2";
+ reg = <0x1fbf0300 0x30>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ //status = "disabled";
+ };
+
+ gpio@1fbf0200 {
+ compatible = "econet,ecnt-gpio";
+ reg = <0x1fbf0200 0x80>;
+ };
+
+ spi_ctrl: spi_controller@1fa10000 {
+ compatible = "econet,ecnt-spi_ctrl";
+ reg = <0x1fa10000 0x140>, //SPI Controller Base
+ <0x00000000 0x1000>; //SPI Controller auto read interrupt test
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ spi_spi2nfi: spi_spi2nfi@1fa11000 {
+ compatible = "econet,ecnt-spi2nfi";
+ reg = <0x1fa11000 0x160>; //NFI2SPI
+ };
+
+ spi_ecc: spi_ecc@1fa12000 {
+ compatible = "econet,ecnt-spi_ecc";
+ reg = <0x1fa12000 0x150>; //NFI ECC
+ };
+
+ frame_engine: frame_engine@1fb50000 {
+ compatible = "econet,ecnt-frame_engine";
+ reg = <0x1fb50000 0x2600>, //FE + PPE
+ <0x1fb54000 0x4000>, //QDMA
+ <0x1fb58000 0x8000>; //SWITCH
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT1 21+16
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT2 39+16
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT3 40+16
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT4 41+16
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT1 22+16
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT2 42+16
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT3 43+16
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT4 44+16
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, // FE ERROR INTR 33+16
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; // PDMA INTR 48+16
+ };
+
+ spi_nor_flash: snor {
+ compatible = "econet,ecnt-snor";
+ spi-controller = <&spi_ctrl>;
+ };
+
+ nand_flash: nand@1fa10000 {
+ compatible = "econet,ecnt-nand";
+ spi-controller = <&spi_ctrl>;
+ spi2nfi = <&spi_spi2nfi>;
+ spi-ecc = <&spi_ecc>;
+ };
+
+ hsdma: dma-controller@1fa01800 {
+ compatible = "econet,en7523-hsdma";
+ reg = <0x1fa01800 0x300>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ dma-requests = <2>;
+ };
+
+ cpu_top@1efb0000 {
+ compatible = "econet,ecnt-cpu_top";
+ reg = <0x1efbc800 0x10>; //CTRL
+ };
+
+ xpon_mac: xpon@1fb64000 {
+ compatible = "econet,ecnt-xpon";
+ reg = <0x1fb64000 0x3e8>,
+ <0x1fb66000 0x23c>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, // XPON MAC INT 26+16
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; // DYINGGASP INT 18+16
+ };
+
+ xhci_hcd: xhci@1fab0000 {
+ compatible = "econet,ecnt-xhci";
+ reg = <0x1fab0000 0x3e00>, //MAC base address
+ <0x1fab3e00 0x100>; //IPPC base address
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pon_phy: pon_phy@1faf0000 {
+ compatible = "econet,ecnt-pon_phy";
+ reg = <0x1faf0000 0x800>, // PON_PHY_ASIC_RG range
+ <0x1fa2ff24 0x4>, // PON_PHY_FPGA_RG_TX_OFF
+ <0x1faf3000 0xfff>, // PON_PHY_ASIC_RG range2
+ <0x1faf4000 0xfff>; // PON_PHY_ASIC_RG range3
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; // XPON_PHY_INTR 27+16
+ };
+
+ pcm@bfbd0000 {
+ compatible = "econet,ecnt-pcm";
+ reg = <0x1fbd0000 0x4fff>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ i2s@1fbe2200 {
+ compatible = "econet,ecnt-i2s";
+ reg = <0x1fbe2200 0xfc>,
+ <0x1fbe2e00 0x114>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pcie_phy: pcie_phy@1fa93700 {
+ compatible = "econet,en7523-pcie_phy";
+ reg = <0x1fa93700 0x568>, //PC0 RG range
+ <0x1fa95700 0x568>; //PC1 RG range
+ };
+
+ pon_hsgmii: pon_hsgmii@1fa65000 {
+ compatible = "econet,ecnt-pon_hsgmii";
+ reg = <0x1fa65100 0x4a0>, //PCS mode1 range
+ <0x1fa65a00 0x1ac>, //PCS mode2 range
+ <0x1fa65e00 0x64>, //AN range
+ <0x1fa66000 0xdc>; //rate adaption range
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; // pon_hsgmii INT 50+16
+ };
+
+ sgmii_p0: sgmii_p0@1fa72000 {
+ compatible = "econet,ecnt-sgmii";
+ reg = <0x1fa72100 0x4a0>, //PCS mode1 range
+ <0x1fa72a00 0x160>, //PCS mode2 range
+ <0x1fa72000 0x64>, //AN range
+ <0x1fa72600 0xdc>, //rate adaption range
+ <0x1fa72c00 0x3b0>; //phya
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; // pc0_hsgmii INT 135+16
+ int_name = "sgmii_pcie0";
+ int_id = <0>;
+ };
+
+ sgmii_p1: sgmii_p1@1fa77000 {
+ compatible = "econet,ecnt-sgmii";
+ reg = <0x1fa77100 0x4a0>, //PCS mode1 range
+ <0x1fa77a00 0x160>, //PCS mode2 range
+ <0x1fa77000 0x64>, //AN range
+ <0x1fa77600 0xdc>, //rate adaption range
+ <0x1fa77c00 0x3b0>; //phya
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; // pc1_hsgmii INT 136+16
+ int_name = "sgmii_pcie1";
+ int_id = <1>;
+ };
+
+ sgmii_u0: sgmii_u0@1fa81000 {
+ compatible = "econet,ecnt-sgmii";
+ reg = <0x1fa81100 0x4a0>, //PCS mode1 range
+ <0x1fa81a00 0x160>, //PCS mode2 range
+ <0x1fa81000 0x64>, //AN range
+ <0x1fa81600 0xdc>, //rate adaption range
+ <0x1fa81c00 0x3b0>; //phya
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; // usb_hsgmii INT 137+16
+ int_name = "sgmii_usb0";
+ int_id = <2>;
+ };
+
+ usb_phy@1fad0000 {
+ compatible = "econet,ecnt-usb_phy";
+ reg = <0x1fad0000 0x1fff>;
+ };
+
+ thermal_phy: thermal_phy@1efbd000 {
+ compatible = "econet,ecnt-thermal_phy";
+ reg = <0x1efbd000 0x0fff>; //ptp_thermal_ctrl
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; // ptp_therm INT 7+16
+ int_name = "ptp_therm";
+ };
+
+/* Generic led driver is not compatible yet
+ gpio0: gpio@1fbf0200 {
+ compatible = "airoha,en7523-gpio";
+ reg = <0x1fbf0204 0x4>,
+ <0x1fbf0200 0x4>,
+ <0x1fbf0220 0x4>,
+ <0x1fbf0214 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio1: gpio@1fbf0270 {
+ compatible = "airoha,en7523-gpio";
+ reg = <0x1fbf0270 0x4>,
+ <0x1fbf0260 0x4>,
+ <0x1fbf0264 0x4>,
+ <0x1fbf0278 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+*/
+
+};
diff --git a/iopsys-econet/dts/rodimus.dts b/iopsys-econet/dts/rodimus.dts
index 6e5b4b533..96854847c 100755
--- a/iopsys-econet/dts/rodimus.dts
+++ b/iopsys-econet/dts/rodimus.dts
@@ -1,539 +1,90 @@
-
-
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
/dts-v1/;
-/ {
- compatible = "econet,en7523";
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <1>;
+#include "en75xx-base.dtsi"
- chosen {
+/ {
+ chosen {
bootargs = "root=/dev/mtdblock3 ro console=ttyS0,115200n8 earlycon init=/sbin/init";
stdout-path = &uart1;
};
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- atf-reserved-memory@80000000 {
- compatible = "econet,en7523-atf-reserved-memory";
- no-map;
- reg = <0x80000000 0x40000>;
- };
-
- npu_reserved: npu_binary@84000000 {
- no-map;
- reg = <0x84000000 0x100000>;
- };
-
- /* pstore memory reservations */
- #include "en7523_pstore.dtsi"
-
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
- core1 {
- cpu = <&cpu1>;
- };
- };
- };
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0>;
- enable-method = "psci";
- clock-frequency = <80000000>;
- next-level-cache = <&L2_0>;
+/* Generic led driver is not compatible yet
+ leds {
+ compatible = "gpio-leds";
+ led1 {
+ label = "green:led1";
+ gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
};
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x1>;
- enable-method = "psci";
- clock-frequency = <80000000>;
- next-level-cache = <&L2_0>;
+ led2 {
+ label = "red:led2";
+ gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
};
-
- L2_0: l2-cache0 {
- compatible = "cache";
+ led3 {
+ label = "blue:led3";
+ gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
};
};
-
- gic: interrupt-controller@09000000 {
- compatible = "arm,gic-v3";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x09000000 0x20000>,
- <0x09080000 0x80000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
-
- its: gic-its@09020000 {
- compatible = "arm,gic-v3-its";
- msi-controller;
- #msi-cell = <1>;
- reg = <0x090200000 0x20000>;
- };
- };
-
-
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- clock-frequency = <25000000>;
- };
-
- pmu {
- //compatible = "arm,armv8-pmuv3";
- compatible = "arm,cortex-a15-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- npu@1e800000 {
- compatible = "econet,ecnt-npu";
- reg = <0x1e800000 0x60000>, //NPU 384K SRAM
- <0x1e900000 0x313000>; //NPU 16K SRAM, Registers
- memory-region = <&npu_reserved>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 102+16 tr done
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 105+16 hadap irq0
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; //mbox2host irq
- };
-
- apb_timer1: apb_timer1@1fbf0100 {
- compatible = "econet,ecnt-timer";
- reg = <0x1fbf0100 0x40>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x40000000>;
- };
-
- rbus@1fa00000 {
- compatible = "econet,ecnt-rbus";
- reg = <0x1fa00000 0x1000>; //RBus Core
- };
-
- sram@1fa40000 {
- compatible = "econet,ecnt-sram";
- reg = <0x1fa40000 0x8000>, //GDMP SRAM
- <0x08000000 0x40000>, //L2C SRAM (only for CPU internal access)
- <0x1EFC0000 0x40000>, //L2C SRAM (only for CPU/NPU/GDMA/SPI/Crypto/WOE external access via pbus)
- <0x1E880000 0x40000>, //L2C SRAM (only for CPU/NPU/HSDMA/PCIE external access via npu_rbus)
- <0x1fbe3000 0x200>; //I2C_SLAVE SRAM
- };
-
- scu@1fb00000 {
- compatible = "econet,ecnt-scu";
- reg = <0x1fb00000 0x960>, //NP SCU
- <0x1fa20000 0x360>, //CHIP SCU
- <0x1fa2FF30 0x10>; //Rbus clk ctl for FPGA
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pcie@0x1fa91000 {
- compatible = "ecnt,pcie-en7523";
- device_type = "pci";
- reg = <0x1fa91000 0x1000>,
- <0x1fa92000 0x1000>,
- <0x1fa90000 0x1000>, /* pcie top*/
- <0x1a100000 0x1000>, /* switch lane */
- <0x1a148000 0x1000>, /* 4, rc0 phy base, for change xtal setting */
- <0x1a14a000 0x1000>; /* 5, rc1 phy base, for change xtal setting */
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, //23+16
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; //24+16
- bus-range = <0x00 0xff>;
- #address-cells = <3>;
- #size-cells = <2>;
- /* change xtal for 40M, default is 25M */
- /* change-xtal; */
- /* disable io coherent for RC and EP default. */
- /*dma-coherent;*/
- ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
-
- pcie0: pcie@0,0 {
- device_type = "pci";
- reg = <0x0000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc0 1>,
- <0 0 0 2 &pcie_intc0 2>,
- <0 0 0 3 &pcie_intc0 3>,
- <0 0 0 4 &pcie_intc0 4>;
- pcie-port = <0>;
- num-lanes = <1>;
- status = "okay";
- wifi0: wifi@0,0 {
- compatible = "mediatek,mt76";
- reg = <0x0000 0 0 0 0>;
- ieee80211-freq-limit = <2400000 2500000>;
- };
- pcie_intc0: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
- };
-
- pcie1: pcie@1,0 {
- device_type = "pci";
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc1 1>,
- <0 0 0 2 &pcie_intc1 2>,
- <0 0 0 3 &pcie_intc1 3>,
- <0 0 0 4 &pcie_intc1 4>;
- pcie-port = <1>;
- num-lanes = <1>;
- status = "okay";
- wifi1: wifi@1,0 {
- compatible = "mediatek,mt76";
- reg = <0x0000 0 0 0 0>;
- ieee80211-freq-limit = <5000000 6000000>;
- };
- pcie_intc1: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
- };
- };
-
- wdma{
- compatible = "en751221,wdma";
- reg = <0x1fa06000 0x400 >,
- <0x1fa06400 0x400 >;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wed{
- compatible = "en751221,wed";
- wed_num = <2>;
- pci_slot_map = <0>, <1>;
- reg = <0x1fa02000 0xb00 >,
- <0x1fa03000 0xb00 >;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wed2{
- compatible = "en751221,wed2";
- wed_num = <2>;
- pci_slot_map = <0>, <1>;
- reg = <0x1fa02000 0xb00 >,
- <0x1fa03000 0xb00 >;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wed_test{
- compatible = "en751221,wed_test";
- wed_num = <2>;
- reg = <0x1fa02b00 0x100 >,
- <0x1fa03b00 0x100 >;
- };
-
-
-
- i2c@1fbf8000 {
- compatible = "econet,ecnt-i2c";
- reg = <0x1fbf8000 0x65>;
- };
-
- gdump@1fbf9000 {
- compatible = "econet,ecnt-gdump";
- reg = <0x1fbf9000 0x84>;
- };
-
- crypto_k@1fb70000 {
- compatible = "econet,ecnt-crypto_k";
- reg = <0x1fb70000 0x804>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- trng@1faa1000 {
- compatible = "econet,ecnt-trng";
- reg = <0x1faa1000 0xc04>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gdma@1fb30000 {
- compatible = "econet,ecnt-gdma";
- reg = <0x1fb30000 0x2b0>;
- };
-
- xsi@1fa60000 {
- compatible = "econet,ecnt-xsi";
- reg = <0x1fa60000 0x300>, //hsgmii ae
- <0x1fa70000 0x300>, //hsgmii pcie0
- <0x1fa71000 0x300>, //hsgmii pcie1
- <0x1fa80000 0x300>; //hsgmii usb
- };
-
- i2c_slave@1fbe3300 {
- compatible = "econet,ecnt-i2c_slave";
- reg = <0x1fbe3300 0x10>;
- dev0_addr = <0x60>;
- dev1_addr = <0x62>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- uart1: serial@1fbf0000 {
- compatible = "econet,ecnt-uart1";
- reg = <0x1fbf0000 0x30>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- //status = "disabled";
- };
- uart2: serial@1fbf0300 {
- compatible = "econet,ecnt-uart2";
- reg = <0x1fbf0300 0x30>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- //status = "disabled";
- };
-/* Generic led driver is not compatible yet
- leds {
- compatible = "gpio-leds";
- led1 {
- label = "green:led1";
- gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
- };
- led2 {
- label = "red:led2";
- gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
- };
- led3 {
- label = "blue:led3";
- gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio0: gpio@1fbf0200 {
- compatible = "airoha,en7523-gpio";
- reg = <0x1fbf0204 0x4>,
- <0x1fbf0200 0x4>,
- <0x1fbf0220 0x4>,
- <0x1fbf0214 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio1: gpio@1fbf0270 {
- compatible = "airoha,en7523-gpio";
- reg = <0x1fbf0270 0x4>,
- <0x1fbf0260 0x4>,
- <0x1fbf0264 0x4>,
- <0x1fbf0278 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
- };
*/
- gpio@1fbf0200 {
- compatible = "econet,ecnt-gpio";
- reg = <0x1fbf0200 0x80>;
- };
-
- spi_ctrl: spi_controller@1fa10000 {
- compatible = "econet,ecnt-spi_ctrl";
- reg = <0x1fa10000 0x140>, //SPI Controller Base
- <0x00000000 0x1000>; //SPI Controller auto read interrupt test
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- spi_spi2nfi: spi_spi2nfi@1fa11000 {
- compatible = "econet,ecnt-spi2nfi";
- reg = <0x1fa11000 0x160>; //NFI2SPI
- };
-
- spi_ecc: spi_ecc@1fa12000 {
- compatible = "econet,ecnt-spi_ecc";
- reg = <0x1fa12000 0x150>; //NFI ECC
- };
-
- frame_engine: frame_engine@1fb50000 {
- compatible = "econet,ecnt-frame_engine";
- reg = <0x1fb50000 0x2600>, //FE + PPE
- <0x1fb54000 0x4000>, //QDMA
- <0x1fb58000 0x8000>; //SWITCH
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT1 21+16
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT2 39+16
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT3 40+16
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT4 41+16
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT1 22+16
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT2 42+16
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT3 43+16
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT4 44+16
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, // FE ERROR INTR 33+16
- <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; // PDMA INTR 48+16
- };
-
- spi_nor_flash: snor {
- compatible = "econet,ecnt-snor";
- spi-controller = <&spi_ctrl>;
- };
-
- nand_flash: nand@1fa10000 {
- compatible = "econet,ecnt-nand";
- spi-controller = <&spi_ctrl>;
- spi2nfi = <&spi_spi2nfi>;
- spi-ecc = <&spi_ecc>;
- };
-
- hsdma: dma-controller@1fa01800 {
- compatible = "econet,en7523-hsdma";
- reg = <0x1fa01800 0x300>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- dma-channels = <2>;
- dma-requests = <2>;
- };
-
- cpu_top@1efb0000 {
- compatible = "econet,ecnt-cpu_top";
- reg = <0x1efbc800 0x10>; //CTRL
- };
-
- xpon_mac: xpon@1fb64000 {
- compatible = "econet,ecnt-xpon";
- reg = <0x1fb64000 0x3e8>,
- <0x1fb66000 0x23c>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, // XPON MAC INT 26+16
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;// DYINGGASP INT 18+16
- };
-
- xhci_hcd: xhci@1fab0000 {
- compatible = "econet,ecnt-xhci";
- reg = <0x1fab0000 0x3e00>, //MAC base address
- <0x1fab3e00 0x100>; //IPPC base address
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pon_phy: pon_phy@1faf0000 {
- compatible = "econet,ecnt-pon_phy";
- reg = <0x1faf0000 0x800>, // PON_PHY_ASIC_RG range
- <0x1fa2ff24 0x4>, // PON_PHY_FPGA_RG_TX_OFF
- <0x1faf3000 0xfff>, // PON_PHY_ASIC_RG range2
- <0x1faf4000 0xfff>; // PON_PHY_ASIC_RG range3
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; // XPON_PHY_INTR 27+16
- };
-
- pcm@bfbd0000 {
- compatible = "econet,ecnt-pcm";
- reg = <0x1fbd0000 0x4fff>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- };
+};
- i2s@1fbe2200 {
- compatible = "econet,ecnt-i2s";
- reg = <0x1fbe2200 0xfc>,
- <0x1fbe2e00 0x114>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pcie_phy: pcie_phy@1fa93700 {
- compatible = "econet,en7523-pcie_phy";
- reg = <0x1fa93700 0x568>, //PC0 RG range
- <0x1fa95700 0x568>; //PC1 RG range
- };
- pon_hsgmii: pon_hsgmii@1fa65000 {
- compatible = "econet,ecnt-pon_hsgmii";
- reg = <0x1fa65100 0x4a0>, //PCS mode1 range
- <0x1fa65a00 0x1ac>, //PCS mode2 range
- <0x1fa65e00 0x64>, //AN range
- <0x1fa66000 0xdc>; //rate adaption range
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; // pon_hsgmii INT 50+16
- };
- sgmii_p0: sgmii_p0@1fa72000 {
- compatible = "econet,ecnt-sgmii";
- reg = <0x1fa72100 0x4a0>, //PCS mode1 range
- <0x1fa72a00 0x160>, //PCS mode2 range
- <0x1fa72000 0x64>, //AN range
- <0x1fa72600 0xdc>, //rate adaption range
- <0x1fa72c00 0x3b0>; //phya
- interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; // pc0_hsgmii INT 135+16
- int_name = "sgmii_pcie0";
- int_id = <0>;
- };
- sgmii_p1: sgmii_p1@1fa77000 {
- compatible = "econet,ecnt-sgmii";
- reg = <0x1fa77100 0x4a0>, //PCS mode1 range
- <0x1fa77a00 0x160>, //PCS mode2 range
- <0x1fa77000 0x64>, //AN range
- <0x1fa77600 0xdc>, //rate adaption range
- <0x1fa77c00 0x3b0>; //phya
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; // pc1_hsgmii INT 136+16
- int_name = "sgmii_pcie1";
- int_id = <1>;
- };
- sgmii_u0: sgmii_u0@1fa81000 {
- compatible = "econet,ecnt-sgmii";
- reg = <0x1fa81100 0x4a0>, //PCS mode1 range
- <0x1fa81a00 0x160>, //PCS mode2 range
- <0x1fa81000 0x64>, //AN range
- <0x1fa81600 0xdc>, //rate adaption range
- <0x1fa81c00 0x3b0>; //phya
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; // usb_hsgmii INT 137+16
- int_name = "sgmii_usb0";
- int_id = <2>;
- };
-
- usb_phy@1fad0000 {
- compatible = "econet,ecnt-usb_phy";
- reg = <0x1fad0000 0x1fff>;
+&pcie0 {
+ device_type = "pci";
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 1>,
+ <0 0 0 2 &pcie_intc0 2>,
+ <0 0 0 3 &pcie_intc0 3>,
+ <0 0 0 4 &pcie_intc0 4>;
+ pcie-port = <0>;
+ num-lanes = <1>;
+ status = "okay";
+
+ wifi0: wifi@0,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ ieee80211-freq-limit = <2400000 2500000>;
+ };
+
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
};
+};
- thermal_phy: thermal_phy@1efbd000 {
- compatible = "econet,ecnt-thermal_phy";
- reg = <0x1efbd000 0x0fff>; //ptp_thermal_ctrl
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; // ptp_therm INT 7+16
- int_name = "ptp_therm";
+&pcie1 {
+ device_type = "pci";
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 1>,
+ <0 0 0 2 &pcie_intc1 2>,
+ <0 0 0 3 &pcie_intc1 3>,
+ <0 0 0 4 &pcie_intc1 4>;
+ pcie-port = <1>;
+ num-lanes = <1>;
+ status = "okay";
+
+ wifi1: wifi@1,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ ieee80211-freq-limit = <5000000 6000000>;
+ };
+
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
};
-
-
};
--
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