From 7683fa58f8518b9fc67affb046527d78ffcd62d1 Mon Sep 17 00:00:00 2001
From: "Wu, Qiming" <qi-ming.wu@intel.com>
Date: Mon, 12 Feb 2018 07:53:51 +0100
Subject: [PATCH] Merge pull request #238 in SW_PON/linux from
bugfix/DRVLIB_SW-395-gswip3.1_driver_development to xrx500
* commit '98d138a640c1875ab91cf77a6d5e7bf82cbea8de':
Pmac Ingress SubId configuration issue Fix
---
.../lantiq/switch-api/gsw_flow_core.c | 46 ++++++++++---------
include/net/switch_api/lantiq_gsw.h | 15 +++---
2 files changed, 31 insertions(+), 30 deletions(-)
diff --git a/drivers/net/ethernet/lantiq/switch-api/gsw_flow_core.c b/drivers/net/ethernet/lantiq/switch-api/gsw_flow_core.c
index 2b77f02ca..aa5f89571 100644
--- a/drivers/net/ethernet/lantiq/switch-api/gsw_flow_core.c
+++ b/drivers/net/ethernet/lantiq/switch-api/gsw_flow_core.c
@@ -12603,17 +12603,19 @@ int GSW_PMAC_IG_CfgSet(void *cdev, GSW_PMAC_Ig_Cfg_t *parm)
}
/* Sub_Interface Id Info from default PMAC header */
- /*TODO:Parameter change in 3.1 Struct*/
- switch(parm->eSubId) {
- case GSW_PMAC_IG_CFG_SRC_DMA_DESC:
- pmtbl.val[4] &= ~(1 << 2);
- break;
- case GSW_PMAC_IG_CFG_SRC_PMAC:
- pmtbl.val[4] |= (1 << 2);
- break;
- default:
- break;
- }
+ switch (parm->eSubId) {
+ case GSW_PMAC_IG_CFG_SRC_DMA_DESC:
+ pmtbl.val[4] &= ~(1 << 2);
+ break;
+
+ case GSW_PMAC_IG_CFG_SRC_PMAC:
+ case GSW_PMAC_IG_CFG_SRC_DEF_PMAC:
+ pmtbl.val[4] |= (1 << 2);
+ break;
+
+ default:
+ break;
+ }
/* Class Enable info from default PMAC header */
if (parm->bClassEna)
@@ -12686,17 +12688,17 @@ int GSW_PMAC_IG_CfgGet(void *cdev, GSW_PMAC_Ig_Cfg_t *parm)
if ((pmtbl.val[4] >> 1) & 0x1)
parm->bSpIdDefault = 1;
- /* Sub_Interface Id Info from default PMAC header */
- /*TODO:Parameter change in 3.1 Struct*/
- SubidMode =((pmtbl.val[4] >> 2) & 0x1);
- switch(SubidMode) {
- case GSW_PMAC_IG_CFG_SRC_DMA_DESC:
- parm->eSubId=GSW_PMAC_IG_CFG_SRC_DMA_DESC;
- break;
- case GSW_PMAC_IG_CFG_SRC_PMAC:
- parm->eSubId=GSW_PMAC_IG_CFG_SRC_PMAC;
- break;
- }
+ /* Sub_Interface Id Info */
+ SubidMode = ((pmtbl.val[4] >> 2) & 0x1);
+ if (SubidMode == 0) {
+ parm->eSubId = GSW_PMAC_IG_CFG_SRC_DMA_DESC;
+ } else {
+ if (gswdev->gipver == LTQ_GSWIP_3_1) {
+ parm->eSubId = GSW_PMAC_IG_CFG_SRC_DEF_PMAC;
+ } else {
+ parm->eSubId = GSW_PMAC_IG_CFG_SRC_PMAC;
+ }
+ }
/* Class Enable info from default PMAC header */
if ((pmtbl.val[4] >> 3) & 0x1)
diff --git a/include/net/switch_api/lantiq_gsw.h b/include/net/switch_api/lantiq_gsw.h
index 36d0645e5..c54fceb89 100644
--- a/include/net/switch_api/lantiq_gsw.h
+++ b/include/net/switch_api/lantiq_gsw.h
@@ -3004,14 +3004,13 @@ typedef struct
/** \brief PMAC Ingress Configuration Source
Source of the corresponding field. */
-typedef enum
-{
- /** Field is from DMA descriptor */
- GSW_PMAC_IG_CFG_SRC_DMA_DESC = 0,
- /** Field is from PMAC header of packet */
- GSW_PMAC_IG_CFG_SRC_PMAC = 1,
- /** Field is from default PMAC header */
- GSW_PMAC_IG_CFG_SRC_DEF_PMAC = 2
+typedef enum {
+ /** Field is from DMA descriptor */
+ GSW_PMAC_IG_CFG_SRC_DMA_DESC = 0,
+ /** Field is from default PMAC header */
+ GSW_PMAC_IG_CFG_SRC_DEF_PMAC = 1,
+ /** Field is from PMAC header of packet */
+ GSW_PMAC_IG_CFG_SRC_PMAC = 2,
} GSW_PMAC_Ig_Cfg_Src_t;
/** \brief Configure the PMAC Ingress Configuration on a given Tx DMA channel to PMAC. (Upto 16 entries).
--
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