From ba9c39c33a05ff2f54307d8ff41c30e282894be0 Mon Sep 17 00:00:00 2001
From: "Zhu, Yi Xin" <yixin.zhu@intel.com>
Date: Fri, 9 Mar 2018 09:34:23 +0100
Subject: [PATCH] Merge pull request #265 in SW_PON/linux from
bugfix/UGW_SW-21213-add-prefix_pinctrl to xrx500
* commit '3130ef003c86bbd244cefe9bdb24de7cc0690252':
add prefix to pinctrl macro of dt-binding head file
---
drivers/pinctrl/pinctrl-equilibrium.c | 39 ++++++++++---------
.../dt-bindings/pinctrl/intel,equilibrium.h | 38 +++++++++---------
2 files changed, 40 insertions(+), 37 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-equilibrium.c b/drivers/pinctrl/pinctrl-equilibrium.c
index fa82bad24..699dff055 100644
--- a/drivers/pinctrl/pinctrl-equilibrium.c
+++ b/drivers/pinctrl/pinctrl-equilibrium.c
@@ -755,7 +755,7 @@ static int eqbr_pinmux_gpio_request(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
- return eqbr_set_pin_mux(pctl, PINMUX_GPIO, pin);
+ return eqbr_set_pin_mux(pctl, EQBR_MUX_GPIO, pin);
}
static const struct pinmux_ops eqbr_pinmux_ops = {
@@ -1119,7 +1119,7 @@ static int pinctrl_setup_from_dt(struct device *dev,
/* Count group number, DON'T support nested child device tree node */
for_each_child_of_node(node, np) {
- if (of_find_property(np, PINCTRL_GROUP, NULL))
+ if (of_find_property(np, EQBR_PINCTRL_GROUP, NULL))
nr_grps++;
}
@@ -1134,12 +1134,12 @@ static int pinctrl_setup_from_dt(struct device *dev,
i = 0;
for_each_child_of_node(node, np) {
- prop = of_find_property(np, PINCTRL_GROUP, NULL);
+ prop = of_find_property(np, EQBR_PINCTRL_GROUP, NULL);
if (!prop)
continue;
/* setup groups */
nr_pins = of_property_count_u32_elems(np,
- PINCTRL_PINS);
+ EQBR_PINCTRL_PINS);
if (nr_pins <= 0) {
dev_err(dev, "No pins in the group: %s\n",
prop->name);
@@ -1151,7 +1151,7 @@ static int pinctrl_setup_from_dt(struct device *dev,
if (!pins)
return -ENOMEM;
for (j = 0; j < nr_pins; j++) {
- if (of_property_read_u32_index(np, PINCTRL_PINS,
+ if (of_property_read_u32_index(np, EQBR_PINCTRL_PINS,
j, &pin_id)) {
dev_err(dev, "Group %s: Read intel pins id failed\n",
grps[i].name);
@@ -1168,7 +1168,7 @@ static int pinctrl_setup_from_dt(struct device *dev,
grps[i].nr_pins = nr_pins;
/* setup functions */
- if (of_property_read_string(np, PINCTRL_FUNCTION,
+ if (of_property_read_string(np, EQBR_PINCTRL_FUNCTION,
&fn_name)) {
/* some groups may not have function, it's OK */
dev_dbg(dev, "Group %s: not function binded!\n",
@@ -1177,7 +1177,7 @@ static int pinctrl_setup_from_dt(struct device *dev,
}
nr_pmx = of_property_count_u32_elems(np,
- PINCTRL_MUX);
+ EQBR_PINCTRL_MUX);
if (nr_pmx <= 0) {
dev_err(dev, "No mux in the group: %s\n",
prop->name);
@@ -1197,7 +1197,8 @@ static int pinctrl_setup_from_dt(struct device *dev,
return -ENOMEM;
if (nr_pmx == 1) {
- if (of_property_read_u32(np, PINCTRL_MUX, &pmx_id)) {
+ if (of_property_read_u32(np,
+ EQBR_PINCTRL_MUX, &pmx_id)) {
dev_err(dev, "Group %s: Read intel mux failed\n",
grps[i].name);
return -EINVAL;
@@ -1206,7 +1207,8 @@ static int pinctrl_setup_from_dt(struct device *dev,
pmx[j] = pmx_id;
} else { /* nr_pmx == nr_pins */
for (j = 0; j < nr_pins; j++) {
- if (of_property_read_u32_index(np, PINCTRL_MUX,
+ if (of_property_read_u32_index(np,
+ EQBR_PINCTRL_MUX,
j, &pmx_id)) {
dev_err(dev, "Group %s: Read intel mux failed\n",
grps[i].name);
@@ -1301,16 +1303,16 @@ static int pinbank_init(struct device_node *np,
unsigned int offset;
struct device *dev = drvdata->dev;
- if (of_property_read_u32(np, PINBANK_REG, &offset)) {
+ if (of_property_read_u32(np, EQBR_PINBANK_REG, &offset)) {
dev_err(dev, "pin bank doesn't have address offset!\n");
return -EFAULT;
}
bank->membase = drvdata->membase + offset;
- if (of_property_read_u32(np, PINBANK_PINBASE, &bank->pin_base)) {
+ if (of_property_read_u32(np, EQBR_PINBANK_PINBASE, &bank->pin_base)) {
dev_err(dev, "pin bank doesn't have pin base ID!\n");
return -EFAULT;
}
- if (of_property_read_u32(np, PINBANK_PINNUM, &bank->nr_pins)) {
+ if (of_property_read_u32(np, EQBR_PINBANK_PINNUM, &bank->nr_pins)) {
dev_err(dev, "pin bank doesn't have pin number!\n");
return -EFAULT;
}
@@ -1349,13 +1351,14 @@ static int pinbank_probe(struct intel_pinctrl_drv_data *drvdata)
}
for_each_child_of_node(np_pad, np_bank) {
- if (of_find_property(np_bank, PINBANK_PROPERTY, NULL)) {
+ if (of_find_property(np_bank, EQBR_PINBANK_PROPERTY, NULL)) {
status = of_get_property(np_bank, "status", &len);
if (status && len > 0 &&
strcmp(status, "disabled") == 0)
continue;
nr_bank++;
- if (of_find_property(np_bank, PINBANK_GPIO_CTRL, NULL))
+ if (of_find_property(np_bank,
+ EQBR_PINBANK_GPIO_CTRL, NULL))
nr_gpio++;
}
}
@@ -1387,7 +1390,7 @@ static int pinbank_probe(struct intel_pinctrl_drv_data *drvdata)
/* Initialize Pin bank */
i = 0;
for_each_child_of_node(np_pad, np_bank) {
- if (of_find_property(np_bank, PINBANK_PROPERTY, NULL)) {
+ if (of_find_property(np_bank, EQBR_PINBANK_PROPERTY, NULL)) {
status = of_get_property(np_bank, "status", &len);
if (status && len > 0 &&
strcmp(status, "disabled") == 0)
@@ -1395,7 +1398,7 @@ static int pinbank_probe(struct intel_pinctrl_drv_data *drvdata)
pinbank_init(np_bank, drvdata, banks + i, i);
prop = of_find_property(np_bank,
- PINBANK_GPIO_CTRL, NULL);
+ EQBR_PINBANK_GPIO_CTRL, NULL);
if (prop) {
phandle = be32_to_cpup(prop->value);
gpio_desc[i].node
@@ -1433,7 +1436,7 @@ static void dbg_print_inited_pin(struct intel_pinctrl_drv_data *drvdata)
if (!(BIT(pin) & bank->aval_pinmap))
continue;
mux = readl(bank->membase + pin * 4);
- if (mux != PINMUX_GPIO)
+ if (mux != EQBR_MUX_GPIO)
dev_dbg(dev, "PIN %u has been set to %u\n",
bank->pin_base + pin, mux);
}
@@ -1491,7 +1494,7 @@ static void pinctrl_pin_reset(struct intel_pinctrl_drv_data *drvdata)
for (pin = 0; pin < gdesc->bank->nr_pins; pin++) {
if (!(BIT(pin) & gdesc->bank->aval_pinmap))
continue;
- eqbr_set_pin_mux(drvdata, PINMUX_GPIO,
+ eqbr_set_pin_mux(drvdata, EQBR_MUX_GPIO,
pin + gdesc->bank->pin_base);
intel_eqbr_gpio_dir_input(&gdesc->chip, pin);
diff --git a/include/dt-bindings/pinctrl/intel,equilibrium.h b/include/dt-bindings/pinctrl/intel,equilibrium.h
index b5667e36f..1c00c255b 100644
--- a/include/dt-bindings/pinctrl/intel,equilibrium.h
+++ b/include/dt-bindings/pinctrl/intel,equilibrium.h
@@ -1,27 +1,27 @@
#ifndef __DT_BINDINGS_PINCTRL_INTEL_EQUILIBRIUM_H_
#define __DT_BINDINGS_PINCTRL_INTEL_EQUILIBRIUM_H_
-#define PINCTRL_DRCC_2_MA 0
-#define PINCTRL_DRCC_4_MA 1
-#define PINCTRL_DRCC_8_MA 2
-#define PINCTRL_DRCC_12_MA 3
+#define EQBR_DRCC_2_MA 0
+#define EQBR_DRCC_4_MA 1
+#define EQBR_DRCC_8_MA 2
+#define EQBR_DRCC_12_MA 3
-#define PINMUX_0 0
-#define PINMUX_1 1
-#define PINMUX_2 2
-#define PINMUX_3 3
-#define PINMUX_4 4
-#define PINMUX_GPIO PINMUX_0
+#define EQBR_MUX_0 0
+#define EQBR_MUX_1 1
+#define EQBR_MUX_2 2
+#define EQBR_MUX_3 3
+#define EQBR_MUX_4 4
+#define EQBR_MUX_GPIO EQBR_MUX_0
-#define PINBANK_PROPERTY "intel,pinbank"
-#define PINBANK_GPIO_CTRL "intel,gpio"
-#define PINBANK_REG "reg"
-#define PINBANK_PINBASE "intel,pinbase"
-#define PINBANK_PINNUM "intel,ngpios"
+#define EQBR_PINBANK_PROPERTY "intel,pinbank"
+#define EQBR_PINBANK_GPIO_CTRL "intel,gpio"
+#define EQBR_PINBANK_REG "reg"
+#define EQBR_PINBANK_PINBASE "intel,pinbase"
+#define EQBR_PINBANK_PINNUM "intel,ngpios"
-#define PINCTRL_GROUP "intel,groups"
-#define PINCTRL_FUNCTION "intel,function"
-#define PINCTRL_PINS "intel,pins"
-#define PINCTRL_MUX "intel,mux"
+#define EQBR_PINCTRL_GROUP "intel,groups"
+#define EQBR_PINCTRL_FUNCTION "intel,function"
+#define EQBR_PINCTRL_PINS "intel,pins"
+#define EQBR_PINCTRL_MUX "intel,mux"
#endif /* __DT_BINDINGS_PINCTRL_INTEL_EQUILIBRIUM_H_ */
--
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