From fef58dd6628c4b8b9c921fae473874fcda6361bf Mon Sep 17 00:00:00 2001
From: Oussama Ghorbel <oussama.ghorbel@iopsys.eu>
Date: Fri, 9 Nov 2018 11:22:53 +0100
Subject: [PATCH] add specific patches for speedport smart3
---
drivers/gpio/gpio-intel-sso.c | 50 ++++-------------------------------
drivers/leds/leds-xrx500.c | 7 ++++-
2 files changed, 11 insertions(+), 46 deletions(-)
diff --git a/drivers/gpio/gpio-intel-sso.c b/drivers/gpio/gpio-intel-sso.c
index b29aec2d5..a8e9a8282 100644
--- a/drivers/gpio/gpio-intel-sso.c
+++ b/drivers/gpio/gpio-intel-sso.c
@@ -22,14 +22,6 @@
#define SSO_CON2 0x2C4
#define SSO_CON3 0x2C8
-/* CON0 */
-#define SWU 31
-#define BLINK_R 30
-#define RZFL 26
-
-/* CON1 */
-#define US 30
-#define US_MASK 3
#define MAX_PIN_NUM_PER_BANK 32
#define MAX_GROUP_NUM 4
#define PINS_PER_GROUP 8
@@ -45,8 +37,8 @@ static const char * const sso_gpio_drv_name = "intel-sso-gpio";
* @gclk: sso gate clock
* @chip: gpio controller chip
* @pins: pin number of the gpio chip
- * @edge: output update clock edge
* @alloc_bitmap: bitmap for allocated pins
+ * @lock: lock to protect register write
*/
struct sso_gpio_priv {
struct regmap *mmap;
@@ -56,7 +48,6 @@ struct sso_gpio_priv {
struct gpio_chip chip;
u32 pins;
int gpio_base;
- int edge;
u32 alloc_bitmap;
};
@@ -65,19 +56,6 @@ static int sso_gpio_writel(struct regmap *map, u32 reg, u32 val)
return regmap_write(map, reg, val);
}
-static int
-sso_gpio_write_mask(struct regmap *map, u32 reg, u32 off, u32 mask, u32 val)
-{
- u32 reg_val;
-
- if (regmap_read(map, reg, ®_val))
- return -EINVAL;
-
- reg_val = (reg_val & ~(mask << off)) | ((val & mask) << off);
-
- return sso_gpio_writel(map, reg, reg_val);
-}
-
static int
sso_gpio_update_bit(struct regmap *map, u32 reg, u32 off, u32 val)
{
@@ -95,7 +73,6 @@ static int sso_gpio_request(struct gpio_chip *chip, unsigned int offset)
return -EINVAL;
priv->alloc_bitmap |= BIT(offset);
- sso_gpio_writel(priv->mmap, DUTY_CYCLE(offset), 0xFF);
return 0;
}
@@ -105,7 +82,6 @@ static void sso_gpio_free(struct gpio_chip *chip, unsigned int offset)
struct sso_gpio_priv *priv = gpiochip_get_data(chip);
priv->alloc_bitmap &= ~BIT(offset);
- sso_gpio_writel(priv->mmap, DUTY_CYCLE(offset), 0x0);
}
static int sso_gpio_get_dir(struct gpio_chip *chip, unsigned int offset)
@@ -126,7 +102,6 @@ static void sso_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
struct sso_gpio_priv *priv = gpiochip_get_data(chip);
sso_gpio_update_bit(priv->mmap, SSO_CPU, offset, value);
- sso_gpio_update_bit(priv->mmap, SSO_CON0, SWU, 1);
}
static int sso_gpio_gc_init(struct sso_gpio_priv *priv,
@@ -153,6 +128,7 @@ static int sso_gpio_gc_init(struct sso_gpio_priv *priv,
static int sso_gpio_hw_init(struct sso_gpio_priv *priv)
{
int i;
+#if 0 // do not reset SSO
/* Clear all duty cycles */
for (i = 0; i < priv->pins; i++) {
@@ -171,25 +147,15 @@ static int sso_gpio_hw_init(struct sso_gpio_priv *priv)
/* NO HW directly controlled pin by default */
if (sso_gpio_writel(priv->mmap, SSO_CON3, 0))
return -ENOTSUPP;
-
+#endif
/* NO BLINK for all pins */
if (sso_gpio_writel(priv->mmap, SSO_CON2, 0))
return -ENOTSUPP;
-
+#if 0 // do not reset sso
/* OUTPUT 0 by default */
if (sso_gpio_writel(priv->mmap, SSO_CPU, 0))
return -ENOTSUPP;
-
- /* update edge */
- if (sso_gpio_update_bit(priv->mmap, SSO_CON0, RZFL, priv->edge))
- return -ENOTSUPP;
-
- /* SW mode by default */
- if (sso_gpio_update_bit(priv->mmap, SSO_CON0, BLINK_R, 0))
- return -ENOTSUPP;
- if (sso_gpio_write_mask(priv->mmap, SSO_CON0, US, US_MASK, 0))
- return -ENOTSUPP;
-
+#endif
return 0;
}
@@ -237,11 +203,6 @@ static int intel_sso_gpio_probe(struct platform_device *pdev)
return -EINVAL;
}
- if (device_property_present(dev, "intel,sso-rising"))
- priv->edge = 0;
- else
- priv->edge = 1;
-
/* gpio mem */
priv->mmap = syscon_node_to_regmap(dev->of_node);
if (IS_ERR(priv->mmap)) {
@@ -261,7 +222,6 @@ static int intel_sso_gpio_probe(struct platform_device *pdev)
priv->pdev = pdev;
platform_set_drvdata(pdev, priv);
- dev_dbg(dev, "sso gpio init success\n");
return 0;
hw_err:
diff --git a/drivers/leds/leds-xrx500.c b/drivers/leds/leds-xrx500.c
index c4fb1b73f..68b3fce78 100755
--- a/drivers/leds/leds-xrx500.c
+++ b/drivers/leds/leds-xrx500.c
@@ -504,5 +504,10 @@ int __init xrx500_sso_init(void)
{
return platform_driver_register(&xrx500_sso_driver);
}
-module_platform_driver(xrx500_sso_driver);
+#if 0
+module_platform_driver(xrx500_sso_driver);
+#else
+/* USB use shift register pin(SOUT6). So, shift register should be initialized before USB, seven_tsai, 20160817 */
+rootfs_initcall(xrx500_sso_init);
+#endif
--
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