brcm63xx: disc: Update WAN-port PHY bsp-patch for BCM SDK 5.04L.02p1

Rebase patch from Arcadyan for WAN-Port PHY for disc to Broadcom SDK
5.04L.02p1. Remove some whitespace issues in the process.

iopsys-brcm63xx-arm/disc/bsp-patches/900-disc-fix-wan-port-phy.patch

+From 3c46855b2a7874b7e8154a2448536f7b459f44e1 Mon Sep 17 00:00:00 2001
 From: Oussama Ghorbel <oussama.ghorbel@iopsys.eu>
 Date: Wed, 24 Feb 2021 11:03:18 +0100
 Subject: [PATCH] disc: fix wan port phy
@@ -5,16 +6,17 @@ Subject: [PATCH] disc: fix wan port phy
 This patch is provided by Arcadyan to fix the external phy issue for
 the board disc
 
+Signed-off-by: Andreas Gnau <andreas.gnau@iopsys.eu>
 ---
  .../opensource/phy/mdio_drv_common.c          |  2 +
- .../opensource/phy/phy_drv_dsl_phy.c          | 99 +++++++++++++++++--
- 2 files changed, 95 insertions(+), 6 deletions(-)
+ .../opensource/phy/phy_drv_dsl_phy.c          | 94 ++++++++++++++++++-
+ 2 files changed, 92 insertions(+), 4 deletions(-)
 
 diff --git a/bcm963xx/bcmdrivers/opensource/phy/mdio_drv_common.c b/bcm963xx/bcmdrivers/opensource/phy/mdio_drv_common.c
-index 86b9ea2a7..a72c86616 100644
+index 9bec899d4..9506ec637 100644
 --- a/bcm963xx/bcmdrivers/opensource/phy/mdio_drv_common.c
 +++ b/bcm963xx/bcmdrivers/opensource/phy/mdio_drv_common.c
-@@ -163,6 +163,8 @@ static void mdio_cfg_clause_mode(uint32_t *p, mdio_clause_t mdio_clause)
+@@ -165,6 +165,8 @@ static void mdio_cfg_clause_mode(uint32_t *p, mdio_clause_t mdio_clause)
      cfg.free_run_clk_enable = 1;
  #if defined(CONFIG_BCM96846) || defined(CONFIG_BCM96856) || defined(CONFIG_BCM96878)
      cfg.mdio_clk_divider = 12;
@@ -24,7 +26,7 @@ index 86b9ea2a7..a72c86616 100644
      cfg.mdio_clause = mdio_clause;
      WRITE_32(p, cfg);
 diff --git a/bcm963xx/bcmdrivers/opensource/phy/phy_drv_dsl_phy.c b/bcm963xx/bcmdrivers/opensource/phy/phy_drv_dsl_phy.c
-index c470b82a0..6acca7032 100644
+index b0cd63194..c157a8c92 100644
 --- a/bcm963xx/bcmdrivers/opensource/phy/phy_drv_dsl_phy.c
 +++ b/bcm963xx/bcmdrivers/opensource/phy/phy_drv_dsl_phy.c
 @@ -36,6 +36,8 @@
@@ -36,10 +38,11 @@ index c470b82a0..6acca7032 100644
   #include "phy_drv_dsl_phy.h"
   #include "phy_drv_brcm.h"
  
-@@ -43,6 +45,78 @@
- 
- DEFINE_MUTEX(bcm_phy_exp_mutex);
+@@ -65,6 +67,79 @@
+  #define IS_SPHY(phy_dev)    0
+ #endif
  
++
 +static int rtl8211f_read_status(phy_dev_t *phy_dev)
 +{
 +    int ret, mode;
@@ -51,25 +54,25 @@ index c470b82a0..6acca7032 100644
 +    phy_dev->pause_tx = 0;
 +
 +    if ((ret = phy_bus_read(phy_dev, 0x01, &val)))
-+	{
++    {
 +        return ret;
-+	}
++    }
 +
 +    phy_dev->link = ((val >> 2) & 0x1);
 +
 +    if (!phy_dev->link)
-+	{
++    {
 +        return 0;
-+	}
++    }
 +
-+	//printk("[PHY_DEBUG] Link is up\n");
++    //printk("[PHY_DEBUG] Link is up\n");
 +
-+	if ((ret = phy_bus_read(phy_dev, 0x1a, &val)))
-+	{
-+		return ret;
-+	}
++    if ((ret = phy_bus_read(phy_dev, 0x1a, &val)))
++    {
++        return ret;
++    }
 +
-+	//printk("[PHY_DEBUG] reg (%d) value: 0x%x\n", 0x1a, val);
++    //printk("[PHY_DEBUG] reg (%d) value: 0x%x\n", 0x1a, val);
 +
 +    mode = ((val >> 3) & 0x7);
 +
@@ -112,63 +115,56 @@ index c470b82a0..6acca7032 100644
 +    return 0;
 +}
 +
- int dsl_phy_exp_rw(phy_dev_t *phy_dev, u32 reg, u16 *v16_p, int rd)
- {
-     u32 bank, offset;
-@@ -166,11 +240,10 @@ int dsl_phy_reset(phy_dev_t *phy_dev)
+ // QGPHYs and SPHY after reset will only advertise speed with full duplex
+ // setup phy to advertise half duplex also.
+ static void _advertise_supported_caps(phy_dev_t *phy_dev)
+@@ -109,9 +184,8 @@ int dsl_phy_reset(phy_dev_t *phy_dev)
              if (++i > 20) {printk("Failed to reset 0x%x\n", phy_dev->addr); return 0;}
              msleep(100);
          }
 -
 -        if (phy_dev->phy_drv->phy_type == PHY_TYPE_DSL_GPHY) {
 -            _advertise_supported_caps(phy_dev);
-+		if (phy_dev->phy_drv->phy_type == PHY_TYPE_DSL_GPHY && phy_dev->addr != CONFIG_ARC_RTL8211F_PHY_ADDR) {
++        if (phy_dev->phy_drv->phy_type == PHY_TYPE_DSL_GPHY && phy_dev->addr != CONFIG_ARC_RTL8211F_PHY_ADDR) {
 +             _advertise_supported_caps(phy_dev);
              brcm_shadow_18_force_auto_mdix_set(phy_dev, 1);
--        }
-+		}
+         }
      }
- 
-     return 1;
-@@ -514,6 +587,13 @@ static void dsl_phy_afe_pll_setup(phy_dev_t *phy_dev)
+@@ -458,6 +532,13 @@ static void dsl_phy_afe_pll_setup(phy_dev_t *phy_dev)
  
  static int phy_init (phy_dev_t *phy_dev)
  {
-+	printk("[PHY_DEBUG] phy_dev->addr: 0x%x\n", phy_dev->addr);
++    printk("[PHY_DEBUG] phy_dev->addr: 0x%x\n", phy_dev->addr);
 +
-+	if(phy_dev->addr == CONFIG_ARC_RTL8211F_PHY_ADDR)		
-+	{
-+		printk("[PHY_DEBUG] External GPHY RTL8211F is configured\n");
-+	}
++    if(phy_dev->addr == CONFIG_ARC_RTL8211F_PHY_ADDR)
++    {
++        printk("[PHY_DEBUG] External GPHY RTL8211F is configured\n");
++    }
 +
      /* 
          Reset External GPHY; 
      */
-@@ -530,8 +610,8 @@ static int phy_init (phy_dev_t *phy_dev)
-             brcm_shadow_18_force_auto_mdix_set(phy_dev, 1);
+@@ -475,7 +556,7 @@ static int phy_init (phy_dev_t *phy_dev)
          }
      }
--
+ 
 -    if (phy_dev->mii_type == PHY_MII_TYPE_RGMII)
-+	
 +    if (phy_dev->mii_type == PHY_MII_TYPE_RGMII && phy_dev->addr != CONFIG_ARC_RTL8211F_PHY_ADDR)
          brcm_shadow_rgmii_init(phy_dev);
  
      if (0 && phy_dev_cable_diag_is_supported(phy_dev))
-@@ -543,6 +623,13 @@ static int phy_init (phy_dev_t *phy_dev)
+@@ -486,6 +567,11 @@ static int phy_init (phy_dev_t *phy_dev)
+ 
  static int _phy_read_status(phy_dev_t *phy_dev)
  {
- #if defined(CONFIG_BCM947622)
-+
-+	if (IsExtPhyId(phy_dev->meta_id) && phy_dev->addr == CONFIG_ARC_RTL8211F_PHY_ADDR)
-+	{
-+		return rtl8211f_read_status(phy_dev);
-+	}
++    if (PhyIsExtPhyId(phy_dev) && phy_dev->addr == CONFIG_ARC_RTL8211F_PHY_ADDR)
++    {
++        return rtl8211f_read_status(phy_dev);
++    }
 +    else /* else if */
-+
      if (phy_dev->mii_type==PHY_MII_TYPE_RGMII)      // update RGMII_IB_STATUS
-     {
-         int ret = brcm_read_status(phy_dev);
+         return brcm_read_status_rgmii_ib_override(phy_dev);
+     else
 -- 
-2.25.1
+2.31.1