GPTC WDT dt parsing support

drivers/clocksource/intel-gptc-timer.c

@@ -100,6 +100,7 @@ struct gptc_timer {
 	u32 irq;
 #define CLK_SRC_FLAG	0x01
 #define CLK_EVT_FLAG	0x02
+#define CLK_WDT_FLAG	0x04
 	u32 flags;
 	u32 frequency;
 	enum gptc_cnt_dir dir;
@@ -335,6 +336,19 @@ static void gptc_per_timer_init(struct gptc_timer *timer)
 		gptc_reload_and_run(timer);
 }
 
+static const char *const gptc_flag_to_str(u32 flags)
+{
+	if (flags & CLK_SRC_FLAG)
+		return "src";
+
+	if (flags & CLK_EVT_FLAG)
+		return "event";
+
+	if (flags & CLK_WDT_FLAG)
+		return "wdt";
+	return "none";
+}
+
 static void gptc_print_config(void)
 {
 	int i;
@@ -346,7 +360,7 @@ static void gptc_print_config(void)
 		pr_debug("timer%d base %p gptcid %d freq %d tid %d cpuid %d irq %d clk %s %s\n",
 			i, timer->base, timer->gptcid, timer->frequency,
 			timer->tid, timer->cpuid, timer->irq,
-			(timer->flags & CLK_SRC_FLAG) ? "src" : "event",
+			gptc_flag_to_str(timer->flags),
 			timer->used ? "used" : "unused");
 	}
 }
@@ -355,7 +369,10 @@ static int gptc_timer_of_init(struct device_node *np)
 {
 	int i, ret;
 	u32 prop;
-	u32 gptcid, nr_evts;
+	u32 gptcid;
+	u32 nr_evts = 0;
+	u32 nr_wdts = 0;
+	u32 nr_srcs = 0;
 	struct resource res;
 	void __iomem *base;
 	struct gptc_timer *timer;
@@ -395,16 +412,17 @@ static int gptc_timer_of_init(struct device_node *np)
 	clk_prepare(fpiclk);
 	freq = clk_get_rate(fpiclk);
 
-	base = of_iomap(np, 0);
-	if (!base) {
-		pr_err("Can't map GPTC registers\n");
-		goto err_iomap;
-	}
-
 	if (!of_property_read_bool(np, "intel,clksrc") &&
-		!of_property_read_bool(np, "intel,clkevt")) {
+		!of_property_read_bool(np, "intel,clkevt") &&
+		!of_property_read_bool(np, "intel,clkwdt")) {
 		ret = -EEXIST;
-		goto err;
+		goto err_fpipre;
+	}
+
+	base = of_iomap(np, 0);
+	if (!base) {
+		pr_err("Can't map GPTC base address\n");
+		goto err_fpipre;
 	}
 
 	if (!of_property_read_u32(np, "intel,clksrc", &prop)) {
@@ -421,52 +439,91 @@ static int gptc_timer_of_init(struct device_node *np)
 		timer->dir = GPTC_COUNT_UP;
 		timer->used = false;
 		gptc_timer_count++;
+		nr_srcs++;
 	}
 
+	/* Parse clock event list */
 	nr_evts = of_property_count_u32_elems(np, "intel,clkevt");
-	if (nr_evts == 0 || nr_evts > TIMER_PER_GPTC) {
-		pr_warn("GPTC%d doesn't provide valid clock events\n", gptcid);
-		ret = -EINVAL;
-		goto err;
-	}
+	if ((nr_evts > 0) && (nr_evts <= TIMER_PER_GPTC)) {
+		ret = of_property_read_u32_array(np, "intel,clkevt",
+			tid, nr_evts);
+		if (ret) {
+			pr_err("GPTC%d failed to get clock event timer list\n",
+				gptcid);
+			goto err;
+		}
 
-	ret = of_property_read_u32_array(np, "intel,clkevt", tid, nr_evts);
-	if (ret) {
-		pr_err("GPTC%d failed to get clock event timer id list\n",
-			gptcid);
-		goto err;
-	}
+		ret = of_property_read_u32_array(np, "intel,cpuid",
+			cpuid, nr_evts);
+		if (ret) {
+			pr_err("GPTC%d failed to get cpu id list\n", gptcid);
+			goto err;
+		}
 
-	ret = of_property_read_u32_array(np, "intel,cpuid", cpuid, nr_evts);
-	if (ret) {
-		pr_err("GPTC%d failed to get cpu id list\n", gptcid);
-		goto err;
+		for (i = 0; i < nr_evts; i++) {
+			timer = &gptc_timer_info[gptc_timer_count];
+			timer->base = base;
+			timer->phy_base = res.start;
+			timer->gptcid = gptcid;
+			timer->tid = tid[i];
+			WARN_ON(timer->tid >= TIMER_PER_GPTC);
+			timer->cpuid = cpuid[i];
+			timer->flags |= CLK_EVT_FLAG;
+			/* Timer ID as index to get irq */
+			timer->irq = irq_of_parse_and_map(np, timer->tid);
+			WARN_ON(timer->irq == 0);
+			timer->frequency = freq;
+			timer->dir = GPTC_COUNT_DOWN;
+			timer->used = false;
+			gptc_timer_count++;
+		}
 	}
 
-	for (i = 0; i < nr_evts; i++) {
-		timer = &gptc_timer_info[gptc_timer_count];
-		timer->base = base;
-		timer->phy_base = res.start;
-		timer->gptcid = gptcid;
-		timer->tid = tid[i];
-		WARN_ON(timer->tid >= TIMER_PER_GPTC);
-		timer->cpuid = cpuid[i];
-		timer->flags |= CLK_EVT_FLAG;
-		/* Timer ID as index to get irq */
-		timer->irq = irq_of_parse_and_map(np, timer->tid);
-		WARN_ON(timer->irq == 0);
-		timer->frequency = freq;
-		timer->dir = GPTC_COUNT_DOWN;
-		timer->used = false;
-		gptc_timer_count++;
+	/* Parse watchdog timer list */
+	nr_wdts = of_property_count_u32_elems(np, "intel,clkwdt");
+	if ((nr_wdts > 0) && (nr_wdts <= TIMER_PER_GPTC)) {
+		ret = of_property_read_u32_array(np, "intel,clkwdt",
+			tid, nr_wdts);
+		if (ret) {
+			pr_err("GPTC%d failed to get wdt timer list\n", gptcid);
+			goto err;
+		}
+
+		ret = of_property_read_u32_array(np, "intel,wdtid",
+			cpuid, nr_wdts);
+		if (ret) {
+			pr_err("GPTC%d failed to get wdt cpu id list\n",
+				gptcid);
+			goto err;
+		}
+
+		for (i = 0; i < nr_wdts; i++) {
+			timer = &gptc_timer_info[gptc_timer_count];
+			timer->base = base;
+			timer->phy_base = res.start;
+			timer->gptcid = gptcid;
+			timer->tid = tid[i];
+			WARN_ON(timer->tid >= TIMER_PER_GPTC);
+			timer->cpuid = cpuid[i];
+			timer->flags |= CLK_WDT_FLAG;
+			/* Timer ID as index to get irq */
+			timer->irq = irq_of_parse_and_map(np, timer->tid);
+			WARN_ON(timer->irq == 0);
+			timer->frequency = freq;
+			timer->dir = GPTC_COUNT_DOWN;
+			timer->used = false;
+			gptc_timer_count++;
+		}
 	}
 
+	pr_debug("GPTC%d nr_srcs %d nr_evts %d nr_wdts %d\n",
+		gptcid, nr_srcs, nr_evts, nr_wdts);
 	/* GPTC level initialization */
 	gptc_global_init(base);
 	return 0;
 err:
 	iounmap(base);
-err_iomap:
+err_fpipre:
 	clk_unprepare(fpiclk);
 	clk_put(fpiclk);
 err_fpiclk: